公开(公告)号：US20160003888A1

公开(公告)日：2016-01-07

申请号：US14321841

申请日：2014-07-02

Applicant: United Microelectronics Corp.

Inventor： Wen-Yin Weng ,  Wei-Heng Hsu ,  Cheng-Tung Huang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: G01R31/26

CPC classification number: G01R31/2621

Abstract: A method of characterizing a device may be used to determine a metal work function of the device according to a threshold voltage, a body effect, and an oxide capacitance of the device. The threshold voltage may be determined according to a current to voltage curve. The oxide capacitance may be determined according to a capacitor to voltage curve.

Abstract translation: 可以使用表征器件的方法来根据器件的阈值电压，体效应和氧化物电容来确定器件的金属功函数。 可以根据电流 - 电压曲线来确定阈值电压。 可以根据电容器对电压曲线来确定氧化物电容。

公开(公告)号：US09722093B1

公开(公告)日：2017-08-01

申请号：US15253896

申请日：2016-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/7869 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969

Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

公开(公告)号：US09929154B2

公开(公告)日：2018-03-27

申请号：US14541085

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/085 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/205 ,  H01L29/165 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8258 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

公开(公告)号：US09793296B2

公开(公告)日：2017-10-17

申请号：US15296027

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02 ,  H01L21/308 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

公开(公告)号：US09508799B2

公开(公告)日：2016-11-29

申请号：US14469566

申请日：2014-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/165 ,  H01L29/78 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 公开了一种用于制造半导体器件的衬底的方法。 该方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。

公开(公告)号：US20160141288A1

公开(公告)日：2016-05-19

申请号：US14541085

申请日：2014-11-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/205 ,  H01L21/02 ,  H01L29/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L27/0886 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/762 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/165 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/7851

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

Abstract translation: 鳍状结构及其形成方法。 该方法包括提供具有第一鳍结构和第二鳍结构的衬底。 接下来，在基板上形成绝缘材料层。 然后，去除第一鳍片结构的一部分以形成第一凹部。 接下来，在第一凹部中依次形成第一缓冲层和第一沟道层。 接下来，去除第二鳍结构的一部分，以形成第二凹部。 然后，顺序地在第二凹部中形成第二缓冲层和第二沟道层，其中第二缓冲层与第一缓冲层不同。

公开(公告)号：US20240162291A1

公开(公告)日：2024-05-16

申请号：US18077203

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-In Wu ,  Yu-Ming Lin ,  Cheng-Tung Huang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7855 ,  H01L29/78696

Abstract: A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.

公开(公告)号：US10312235B2

公开(公告)日：2019-06-04

申请号：US15892366

申请日：2018-02-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Wei-Heng Hsu ,  Yu-Ming Lin ,  Ya-Ru Yang

IPC: H01L21/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8258 ,  H01L27/088 ,  H01L27/092 ,  H01L29/165 ,  H01L29/205 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure. Next, an insulation material layer is formed on the substrate. Then, a portion of the first fin structure is removed, to form a first recess. Following this, a first buffer layer and a first channel layer are formed sequentially in the first recess. Next, a portion of the second fin structure is removed, to form a second recess. Then, a second buffer layer and a second channel layer are formed in the second recess sequentially, wherein the second buffer layer is different from the first buffer layer.

公开(公告)号：US20180006129A1

公开(公告)日：2018-01-04

申请号：US15628592

申请日：2017-06-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/516 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969 ,  H01L29/7869

Abstract: A transistor includes a semiconductor channel layer, a gate structure, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The gate structure is disposed on the semiconductor channel layer. The gate insulation layer is disposed between the gate structure and the semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the gate structure. The ferroelectric material layer is disposed between the internal electrode and the gate structure. A spacer is disposed on the semiconductor channel layer, and a trench surrounded by the spacer is formed above the semiconductor channel layer. The ferroelectric material layer is disposed in the trench, and the gate structure is at least partially disposed outside the trench. The ferroelectric material layer in the transistor of the present invention is used to enhance the electrical characteristics of the transistor.

公开(公告)号：US20160064485A1

公开(公告)日：2016-03-03

申请号：US14469566

申请日：2014-08-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Yin Weng ,  Cheng-Tung Huang ,  Ya-Ru Yang ,  Yi-Ting Wu ,  Yu-Ming Lin ,  Jen-Yu Wang

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L27/1207 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/3081 ,  H01L21/76251 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for fabricating substrate of a semiconductor device is disclosed. The method includes the steps of: providing a first silicon layer; forming a dielectric layer on the first silicon layer; bonding a second silicon layer to the dielectric layer; removing part of the second silicon layer and part of the dielectric layer to define a first region and a second region on the first silicon layer, wherein the remaining of the second silicon layer and the dielectric layer are on the second region; and forming an epitaxial layer on the first region of the first silicon layer, wherein the epitaxial layer and the second silicon layer comprise same crystalline orientation.

Abstract translation: 公开了一种用于制造半导体器件的衬底的方法。 该方法包括以下步骤：提供第一硅层; 在所述第一硅层上形成介电层; 将第二硅层接合到介电层; 去除所述第二硅层的一部分和所述介电层的一部分以限定所述第一硅层上的第一区域和第二区域，其中所述第二硅层和所述介电层的剩余部分位于所述第二区域上; 以及在所述第一硅层的所述第一区上形成外延层，其中所述外延层和所述第二硅层包含相同的晶体取向。