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公开(公告)号：US09722604B2
公开(公告)日：2017-08-01
申请号：US14634646
申请日：2015-02-27
Applicant: Xilinx, Inc.
Inventor： Junho Cho
IPC: H03K19/00 , H03K19/0944 , H03K19/0175
CPC classification number: H03K19/0013 , H03K19/017545 , H03K19/09432 , H03K19/09441
Abstract: In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.
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公开(公告)号：US11277144B1
公开(公告)日：2022-03-15
申请号：US16840533
申请日：2020-04-06
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Parag Upadhyaya
Abstract: An apparatus for reducing or removing a direct current (DC) offset voltage from one or more analog signals is disclosed. An analog signal may be received by an integrator. The integrator may integrate the analog signal to determine a DC offset error signal. The apparatus may integrate, invert, and amplify the DC offset error signal to provide an analog correction signal. The analog correction signal may be inverted and subtracted from the analog signal. In some implementations, the apparatus may include multiple, independent circuits to reduce or remove DC offset voltages from differential signals.
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公开(公告)号：US20160254813A1
公开(公告)日：2016-09-01
申请号：US14634646
申请日：2015-02-27
Applicant: Xilinx, Inc.
Inventor： Junho Cho
IPC: H03K19/00 , H03K17/687 , H03K19/0175 , H03K19/0944
CPC classification number: H03K19/0013 , H03K19/017545 , H03K19/09432 , H03K19/09441
Abstract: In one example, a current-mode logic (CML) circuit includes a differential transistor pair having a differential input port configured to receive a differential input voltage, a bias port configured for coupling to a current source, and a differential output port. The CML circuit further includes a load circuit coupled to the differential output port. The load circuit includes an active inductive load, a cross-coupled transistor pair, and a switch coupled between the cross-coupled transistor pair and the differential output.
Abstract translation: 在一个示例中，电流模式逻辑（CML）电路包括差分晶体管对，其具有被配置为接收差分输入电压的差分输入端口，被配置为耦合到电流源的偏置端口和差分输出端口。 CML电路还包括耦合到差分输出端口的负载电路。 负载电路包括有源电感负载，交叉耦合晶体管对和耦合在交叉耦合晶体管对和差分输出之间的开关。
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Patent Agency Ranking
公开(公告)号：US09906232B1
公开(公告)日：2018-02-27
申请号：US15455915
申请日：2017-03-10
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Parag Upadhyaya , Chi Fung Poon
CPC classification number: H04L7/0087 , H03M1/007 , H03M1/40 , H03M1/462 , H04B1/0014 , H04L27/0002
Abstract: An example successive approximation (SAR) analog-to-digital converter (ADC) includes: a track-and-hold (T/H) circuit configured to receive an analog input signal; a digital-to-analog converter (DAC); an adder having inputs coupled to outputs of the T/H circuit and the DAC; a comparison circuit coupled to an output of the adder and configured to perform a comparison operation; and a control circuit, coupled to an output of the comparison circuit, configured to: receive a selected resolution; gate the comparison operation of the comparison circuit based on the selected resolution; and generate a digital output signal having the selected resolution.
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公开(公告)号：US09698970B1
公开(公告)日：2017-07-04
申请号：US15060342
申请日：2016-03-03
Applicant: Xilinx, Inc.
Inventor： Junho Cho
CPC classification number: H03K5/135 , H03K5/131 , H03K5/14 , H03K2005/00052 , H03K2005/00065 , H03K2005/00071 , H03L7/081
Abstract: An example clock delivery system includes a phase-locked loop (PLL) configured to generate a plurality of input clocks, a phase interpolator configured to receive the plurality of input clocks and generate a plurality of output clocks, and a clock data recovery (CDR) circuit configured to receive the plurality of output clocks. The phase interpolator includes a decoder having a plurality of inputs configured to receive binary codes and a respective plurality of outputs configured to output thermometer codes, and a mixer circuitry segmented into a plurality of unit circuits that are enabled or disabled based on bits of the thermometer codes.
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公开(公告)号：US09667236B1
公开(公告)日：2017-05-30
申请号：US15011012
申请日：2016-01-29
Applicant: Xilinx, Inc.
Inventor： Junho Cho , Jinyung Namkoong
CPC classification number: H03K5/13 , H03K2005/00052 , H03M1/742
Abstract: A phase interpolator includes: a digital-to-analog converter to generate bias signals associated with phase signals; a multiplexer having an input interface and an output interface, wherein the digital-to-analog converter is coupled to the input interface of the multiplexer; a first current source; and a second current source; wherein the digital-to-analog converter is configured to provide bleeder current signals to the first current source and the second current source while bypassing the multiplexer.
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公开(公告)号：US11984817B2
公开(公告)日：2024-05-14
申请号：US16814626
申请日：2020-03-10
Applicant: XILINX, INC.
Inventor： Junho Cho , Kevin Zheng , Parag Upadhyaya
IPC: H02M7/483
CPC classification number: H02M7/483 , H02M7/4835
Abstract: An example continuous time linear equalizer (CTLE) includes a first inverter; a second inverter having an input to receive an input signal; a capacitor coupled between an input of the first inverter and the input of the second inverter; a resistor coupled between a common-mode voltage and the input of the first inverter; a third inverter having an output to provide an output signal; and a node comprising an output of the first inverter, an output of the second inverter, an input of the third inverter, and the output of the third inverter.
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公开(公告)号：US10291192B1
公开(公告)日：2019-05-14
申请号：US15916887
申请日：2018-03-09
Applicant: Xilinx, Inc.
Inventor： Ronan Casey , Chi Fung Poon , Ilias Chlis , Junho Cho
Abstract: Apparatus and associated methods relate to a peaking module fabricated on a semiconductor substrate including a follower circuit driving a series peaking circuit-branch, the module configured to extend the bandwidth of a track-and-hold circuit. In an illustrative example, the series peaking circuit-branch may include an inductive element. One or more tracks on a metal interconnect above the semiconductor substrate may form the inductive element, for example. In some examples, one or more peaking modules may be combined creating a customized frequency response. In some examples, one or more combined peaking modules may be adjusted by a controller providing dynamic frequency response customization during operation. The follower circuits may employ constant current biasing and/or constant-gm biasing to provide substantial immunity to process, temperature and voltage variations, for example. Various implementations of series peaking circuit-branch pre-emphasis may advantageously extend overall bandwidth of various circuits (e.g., high-speed track-and-hold circuits).
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