公开(公告)号：US20170063580A1

公开(公告)日：2017-03-02

申请号：US14834276

申请日：2015-08-24

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev

IPC: H04L25/08 ,  H04L25/49 ,  H04L25/06 ,  H04L27/04

CPC classification number: H04L25/085 ,  H03K19/018528 ,  H04L25/06 ,  H04L25/4917 ,  H04L27/04

Abstract: A transmitter circuit for generating a modulated signal in a transmitter of an integrated circuit is described. The transmitter circuit comprises a multiplexing stage having a multiplexing circuit configured to receive a differential input signal and to generate a differential output signal at a first output node of a first current path and at a second output node of a second current path, the multiplexing stage having a gain circuit configured to increase the swing of the differential output signal generated at the first output node and the second output node. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

Abstract translation: 描述了用于在集成电路的发射机中产生调制信号的发射机电路。 发射机电路包括复用级，复用级具有被配置为接收差分输入信号并且在第一电流路径的第一输出节点处和在第二电流路径的第二输出节点处产生差分输出信号的复用电路，复用级 具有增益电路，其被配置为增加在第一输出节点和第二输出节点处产生的差分输出信号的摆幅。 还公开了一种在集成电路的发射机中产生调制信号的方法。

公开(公告)号：US09294091B1

公开(公告)日：2016-03-22

申请号：US14056895

申请日：2013-10-17

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev ,  Hsung Jai Im

IPC: H03K3/03 ,  H03K19/003 ,  H03K3/015

CPC classification number: H03K19/00315 ,  H03K3/015 ,  H03K3/0315 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/09432

Abstract: An integrated circuit and method for providing a differential transmission line driver are disclosed. One embodiment of the differential transmission line driver comprises a current mode logic (CML) stage, and a cross-coupled n-channel enhancement type metal-oxide semiconductor field-effect transistor (NMOS) stage, wherein the cross-coupled NMOS stage provides a feedback current to the CML stage, where each output voltage of the differential transmission line driver is characterized by symmetrical rising and falling edges.

Abstract translation: 公开了一种用于提供差分传输线驱动器的集成电路和方法。 差分传输线驱动器的一个实施例包括电流模式逻辑（CML）级和交叉耦合的n沟道增强型金属氧化物半导体场效应晶体管（NMOS）级，其中交叉耦合NMOS级提供 反馈电流到CML级，其中差分传输线驱动器的每个输出电压的特征在于对称的上升和下降沿。

公开(公告)号：US09832048B2

公开(公告)日：2017-11-28

申请号：US14834276

申请日：2015-08-24

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev

IPC: H04L25/08 ,  H04L25/06 ,  H04L25/49 ,  H04L27/04 ,  H03K19/0185

CPC classification number: H04L25/085 ,  H03K19/018528 ,  H04L25/06 ,  H04L25/4917 ,  H04L27/04

Abstract: A transmitter circuit for generating a modulated signal in a transmitter of an integrated circuit is described. The transmitter circuit comprises a multiplexing stage having a multiplexing circuit configured to receive a differential input signal and to generate a differential output signal at a first output node of a first current path and at a second output node of a second current path, the multiplexing stage having a gain circuit configured to increase the swing of the differential output signal generated at the first output node and the second output node. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

公开(公告)号：US09607948B2

公开(公告)日：2017-03-28

申请号：US14674321

申请日：2015-03-31

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Vassili Kireev

IPC: H01L25/00 ,  H01L23/538 ,  H01L27/02 ,  H03K19/173

CPC classification number: H01L23/5382 ,  H01L23/3121 ,  H01L23/5386 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107 ,  H03K19/1732 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

公开(公告)号：US20140266434A1

公开(公告)日：2014-09-18

申请号：US13828943

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev

IPC: H01F17/00 ,  H01F41/04 ,  H03F3/04

CPC classification number: H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F3/04 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described.

Abstract translation: 描述用于在集成电路中实现增益级的电路。 电路包括形成在第一多个金属层中的第一电感器; 形成在第二多个金属层中的第二电感器，所述第二电感器耦合到所述第一电感器的中心抽头; 并且其中所述第二电感器的直径小于所述第一电感器的直径。 还描述了在集成电路中实现增益级的方法。

公开(公告)号：US09674015B2

公开(公告)日：2017-06-06

申请号：US14798364

申请日：2015-07-13

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev ,  Yu Liao

IPC: H04L25/49 ,  H03K5/24 ,  H03K19/094 ,  H03K19/177

CPC classification number: H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

公开(公告)号：US09379663B1

公开(公告)日：2016-06-28

申请号：US14665201

申请日：2015-03-23

Applicant: Xilinx, Inc.

Inventor： Somnath Kundu ,  Vassili Kireev

IPC: H03B5/12

CPC classification number: H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1296 ,  H03B2200/0074

Abstract: In one example, an oscillator circuit includes: a master oscillator comprising a master LC tank coupled to a master active circuit, the master LC tank including a primary winding of a transformer and a capacitance; a slave oscillator comprising a slave LC tank coupled to a slave active circuit, the slave LC tank including a secondary winding of the transformer and a capacitance; and a first pair of coupling transistors and a second pair of coupling transistors each coupling the master oscillator to the slave oscillator. Gates of the first pair of coupling transistors are coupled to the master oscillator through a switch. Gates of the second pair of coupling transistors are coupled to the master oscillator through respective ninety-degree phase shifters and the switch.

Abstract translation: 在一个示例中，振荡器电路包括：主振荡器，包括耦合到主有源电路的主LC箱，主LC箱包括变压器的初级绕组和电容; 从振荡器，包括耦合到从动电路的从LC液晶盒，从LC液晶盒包括变压器的次级绕组和电容; 以及第一对耦合晶体管和第二对耦合晶体管，每个耦合晶体管将主振荡器耦合到从振荡器。 第一对耦合晶体管的栅极通过开关耦合到主振荡器。 第二对耦合晶体管的栅极通过相应的九十位移相器和开关耦合到主振荡器。

公开(公告)号：US20170019278A1

公开(公告)日：2017-01-19

申请号：US14798364

申请日：2015-07-13

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev ,  Yu Liao

IPC: H04L25/49

CPC classification number: H04L25/4919 ,  H03K5/2481 ,  H03K19/09425 ,  H03K19/17788 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/4917

Abstract: A circuit for generating a modulated signal in a transmitter of an integrated circuit is disclosed. The circuit comprises a transmitter driver circuit having a first current path for receiving a first input signal of a pair of differential input signals and a second current path for receiving a second input signal of the pair of differential input signals, the transmitter driver circuit comprising a tail current path coupled to each of the first current path and the second current path; a first current source coupled between a first reference voltage and ground, wherein a first current of the first current source is proportional to the tail current of the tail current path; a first pull-up current source coupled between the first reference voltage and a first output node of the transmitter driver circuit; and a second pull-up current source coupled between the first reference voltage and a second output node of the transmitter driver circuit. A method of generating a modulated signal in a transmitter of an integrated circuit is also disclosed.

Abstract translation: 公开了一种用于在集成电路的发射机中产生调制信号的电路。 该电路包括具有用于接收一对差分输入信号的第一输入信号的第一电流路径和用于接收该对差分输入信号的第二输入信号的第二电流路径的发射器驱动器电路，该发射器驱动电路包括： 耦合到第一电流路径和第二电流路径中的每一个的尾部电流路径; 耦合在第一参考电压和地之间的第一电流源，其中所述第一电流源的第一电流与所述尾电流路径的尾电流成比例; 耦合在所述第一参考电压和所述发射器驱动器电路的第一输出节点之间的第一上拉电流源; 以及耦合在所述发射器驱动器电路的所述第一参考电压和第二输出节点之间的第二上拉电流源。 还公开了一种在集成电路的发射机中产生调制信号的方法。

公开(公告)号：US09048017B2

公开(公告)日：2015-06-02

申请号：US13828943

申请日：2013-03-14

Applicant: Xilinx, Inc.

Inventor： Vassili Kireev

IPC: H01F17/00 ,  H01F41/04 ,  H03F3/04 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01F17/0013 ,  H01F41/041 ,  H01L23/5227 ,  H01L28/10 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03F3/04 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described.

Abstract translation: 描述用于在集成电路中实现增益级的电路。 电路包括形成在第一多个金属层中的第一电感器; 形成在第二多个金属层中的第二电感器，所述第二电感器耦合到所述第一电感器的中心抽头; 并且其中所述第二电感器的直径小于所述第一电感器的直径。 还描述了在集成电路中实现增益级的方法。

公开(公告)号：US20160293548A1

公开(公告)日：2016-10-06

申请号：US14674321

申请日：2015-03-31

Applicant: Xilinx, Inc.

Inventor： James Karp ,  Vassili Kireev

IPC: H01L23/538 ,  H01L27/02

CPC classification number: H01L23/5382 ,  H01L23/3121 ,  H01L23/5386 ,  H01L25/00 ,  H01L25/0655 ,  H01L25/18 ,  H01L27/0207 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/19107 ,  H03K19/1732 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Various example implementations are directed to circuits and methods for inter-die communication on a multi-die integrated circuit (IC) package. According to an example implementation, an IC package includes a first semiconductor die having a plurality of communication circuits for communicating data over respective data terminals of the package. The package also includes a second semiconductor die having N contacts for communicating data to and from the semiconductor die. The second semiconductor die includes a logic circuit configured to communicate M parallel data signals with one or more other semiconductor dies of the package, wherein M>N. The second semiconductor die also includes a plurality of serializer circuits, each configured to serialize data from a respective subset of the plurality of the M signal lines to produce serialized data and provide the serialized data to a respective one of the contacts.

Abstract translation: 各种示例性实现涉及用于多芯片集成电路（IC）封装上的管芯间通信的电路和方法。 根据示例实现，IC封装包括具有用于在封装的各个数据端子上传送数据的多个通信电路的第一半导体管芯。 封装还包括具有N个触点的第二半导体管芯，用于将数据传送到半导体管芯和从半导体管芯传送数据。 第二半导体管芯包括被配置为将M个并行数据信号与封装的一个或多个其它半导体管芯通信的逻辑电路，其中M> N。 第二半导体裸片还包括多个串行化器电路，每个串行器电路被配置为串行化来自多个M个信号线的相应子集的数据，以产生串行数据并将序列化数据提供给相应的一个触点。