公开(公告)号：US06926818B1

公开(公告)日：2005-08-09

申请号：US09961557

申请日：2001-09-24

申请人： Yih-Ann Lin ,  Tung-Heng Shie ,  Kai-Ming Ching ,  Sheng-Liang Pan ,  Kuo-Liang Lu

发明人： Yih-Ann Lin ,  Tung-Heng Shie ,  Kai-Ming Ching ,  Sheng-Liang Pan ,  Kuo-Liang Lu

IPC分类号： C25D5/02

CPC分类号： C25D5/022 ,  H01L2224/0401 ,  H01L2224/05557

摘要： A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug. The patterned dry film resist is removed from the conductive structure. The conductive plug is reflowed to form the bump structure.

摘要翻译： 通过使用电镀液形成凸点结构的方法，包括以下步骤。 提供具有上覆导电结构的基板。 在导电结构上形成图案化的干膜抗蚀剂。 图案化的干膜抗蚀剂具有暴露导电结构的一部分的沟槽。 在界面处附着在导电结构上的图案化的干膜抗蚀剂。 通过增加图案化的干膜抗蚀剂在界面处的导电结构的粘附性的处理来处理该结构。 通过使用电镀溶液，导电插塞在沟槽内的导电结构的暴露部分之上。 图案化的干膜抗蚀剂在界面处增加了对导电结构的粘附，防止电镀溶液在形成导电插塞期间渗透图案化的干膜抗蚀剂和导电结构的界面。 从导电结构去除图案化的干膜抗蚀剂。 导电塞被回流以形成凸块结构。

公开(公告)号：US06468704B1

公开(公告)日：2002-10-22

申请号：US09835027

申请日：2001-04-16

申请人： Chi-Hung Liao ,  Yih-Ann Lin ,  Sheng-Liang Pan ,  Cheng-Yu Chu ,  Kuo-Liang Lu ,  Yu Hsi Wang

发明人： Chi-Hung Liao ,  Yih-Ann Lin ,  Sheng-Liang Pan ,  Cheng-Yu Chu ,  Kuo-Liang Lu ,  Yu Hsi Wang

IPC分类号： G03F900

CPC分类号： G03F9/7046 ,  G03F9/7076 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for alignment to an alignment mark array within a patterned electronic material layer, formed on a substrate employed in a microelectronics fabrication, with improved registration accuracy of a subsequent step-and-repeat photomask pattern. There is first provided a substrate upon which is formed a patterned microelectronics layer containing an alignment mark array. There is then formed over the substrate and patterned layer, covering over the alignment marks, a subsequent layer or layers which may be of opaque material. In order to align properly a patterned photomask for patterning the overlying layer by means of conventional photolithography, the alignment mark array is located by first scanning with a laser light source contained within a step-and-repeat apparatus containing the patterned photomask and detecting the optical radiation signal scattered from the alignment mark array. The accuracy of location may be enhanced by rotating the orientation of the alignment mark array with respect to the direction of scanning with the laser light source by 90 degrees to render the subsequent orientation orthogonal to the first orientation, and then repeating the scanning operation. The altered nature of the back-scattered light signal from the orthogonal scanning direction provides additional information for improving the precision of location and alignment.

摘要翻译： 一种用于对准图案化电子材料层内的对准标记阵列的方法，其形成在微电子制造中使用的衬底上，具有改进的后续步进重复光掩模图案的配准精度。 首先设置有基板，在其上形成包含对准标记阵列的图案化微电子层。 然后在衬底和图案化层上形成覆盖对准标记的后续层或层，其可以是不透明材料。 为了适当地对准用于通过常规光刻法图案化上覆层的图案化光掩模，通过首先用包含在包含图案化光掩模的步进重复设备中的激光源进行扫描来定位对准标记阵列，并且检测光学 从对准标记阵列散射的辐射信号。 可以通过将对准标记阵列的方向相对于激光光源的扫描方向旋转90度来使得随后的方向与第一方位正交，然后重复扫描操作来提高位置的精度。 来自正交扫描方向的反向散射光信号的改变性质提供了用于提高位置和对准精度的附加信息。

公开(公告)号：US08551837B2

公开(公告)日：2013-10-08

申请号：US13408016

申请日：2012-02-29

申请人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

发明人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

IPC分类号： H01L21/8242

CPC分类号： H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

摘要翻译： 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US07833853B2

公开(公告)日：2010-11-16

申请号：US12339483

申请日：2008-12-19

申请人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

发明人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Joseph Lin ,  Jr Jung Lin ,  Yu Chao Lin ,  Chao-Cheng Chen ,  Kuo-Tai Huang

IPC分类号： H01L21/28

CPC分类号： H01L29/7848 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636

摘要： Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

摘要翻译： 提供了一种半导体制造方法，包括允许在制造过程期间限定和/或修改栅极结构高度的工艺步骤。 栅极结构高度可以在制造期间的一个或多个阶段被修改（例如减小），通过蚀刻包括在栅极结构中的多晶硅层的一部分。 该方法包括在衬底上形成覆盖层并覆盖栅极结构。 将涂层回蚀刻以露出栅极结构的一部分。 蚀刻栅极结构（例如，多晶硅）以降低栅极结构的高度。

公开(公告)号：US20100068876A1

公开(公告)日：2010-03-18

申请号：US12405965

申请日：2009-03-17

申请人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

发明人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin ,  Yu Chao Lin

IPC分类号： H01L21/28

CPC分类号： H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

摘要翻译： 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US09633905B2

公开(公告)日：2017-04-25

申请号：US13452516

申请日：2012-04-20

申请人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

发明人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L21/762

CPC分类号： H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

摘要： A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

公开(公告)号：US20130277759A1

公开(公告)日：2013-10-24

申请号：US13452516

申请日：2012-04-20

申请人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

发明人： Ryan Chia-Jen Chen ,  Yih-Ann Lin ,  Chia Tai Lin ,  Chao-Cheng Chen

IPC分类号： H01L29/06 ,  H01L21/762 ,  H01L27/088

CPC分类号： H01L21/823431 ,  H01L21/3081 ,  H01L21/76232 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/6681

摘要： A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

摘要翻译： 一种器件包括半导体衬底和彼此平行的多个半导体鳍片，其中多个半导体鳍片是半导体衬底的一部分。 浅沟槽隔离（STI）区域位于多个半导体鳍片的一侧。 STI区域具有顶表面和非平坦底表面，其中多个半导体鳍片在STI区域的顶表面之上。

公开(公告)号：US08258588B2

公开(公告)日：2012-09-04

申请号：US12757241

申请日：2010-04-09

申请人： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

发明人： Yu Chao Lin ,  Jr Jung Lin ,  Yih-Ann Lin ,  Jih-Jse Lin ,  Chao-Cheng Chen ,  Ryan Chia-Jen Chen ,  Weng Chang

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/4983 ,  H01L29/6656

摘要： An exemplary structure for a gate structure of a field effect transistor comprises a gate electrode; a gate insulator under the gate electrode having footing regions on opposing sides of the gate electrode; and a sealing layer on sidewalls of the gate structure, wherein a thickness of lower portion of the sealing layer overlying the footing regions is less than a thickness of upper portion of the sealing layer on sidewalls of the gate electrode, whereby the field effect transistor made has almost no recess in the substrate surface.

摘要翻译： 场效应晶体管的栅极结构的示例性结构包括栅电极; 栅电极下方的栅极绝缘体，在栅电极的相对侧具有基极区域; 以及在所述栅极结构的侧壁上的密封层，其中覆盖所述基底区域的所述密封层的下部的厚度小于所述栅极电极的侧壁上的所述密封层的上部的厚度，由此所述场效应晶体管 在基板表面几乎没有凹陷。

公开(公告)号：US20120164822A1

公开(公告)日：2012-06-28

申请号：US13408016

申请日：2012-02-29

申请人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

发明人： Yih-Ann Lin ,  Ryan Chia-Jen Chen ,  Chien-Hao Chen ,  Kuo-Tai Huang ,  Yi-Hsing Chen ,  Jr Jung Lin

IPC分类号： H01L21/28

CPC分类号： H01L21/823828 ,  H01L21/3221 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517

摘要： Methods of fabricating semiconductor devices with high-k/metal gate features are disclosed. In some instances, methods of fabricating semiconductor devices with high-k/metal gate features are disclosed that prevent or reduce high-k/metal gate contamination of non-high-k/metal gate wafers and production tools. In some embodiments, the method comprises forming an interfacial layer over a semiconductor substrate on a front side of the substrate; forming a high-k dielectric layer and a capping layer over the interfacial layer; forming a metal layer over the high-k and capping layers; forming a polysilicon layer over the metal layer; and forming a dielectric layer over the semiconductor substrate on a back side of the substrate.

摘要翻译： 公开了制造具有高k /金属栅极特征的半导体器件的方法。 在一些情况下，公开了制造具有高k /金属栅极特征的半导体器件的方法，其防止或减少非高k /金属栅极晶片和生产工具的高k /金属栅极污染。 在一些实施例中，该方法包括在衬底的前侧上的半导体衬底上形成界面层; 在界面层上形成高k电介质层和覆盖层; 在高k和覆盖层上形成金属层; 在所述金属层上形成多晶硅层; 以及在所述衬底的背面上在所述半导体衬底上形成介电层。

公开(公告)号：US08163625B2

公开(公告)日：2012-04-24

申请号：US12753972

申请日：2010-04-05

申请人： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

发明人： Yih-Ann Lin ,  Hao-Ming Lien ,  Ryan Chia-Jen Chen ,  Jr Jung Lin ,  Yu Chao Lin ,  Chih-Han Lin

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： The disclosure relates to integrated circuit fabrication, and more particularly to an electronic device with an isolation structure having almost no divot. An exemplary method for fabricating an isolation structure, comprising: forming a pad oxide layer over a top surface of a substrate; forming an opening in the pad oxide layer, exposing a portion of the substrate; etching the exposed portion of the substrate, forming a trench in the substrate; filling the trench with an insulator; exposing a surface of the pad oxide layer and a surface of the insulator to a vapor mixture including at least an NH3 and a fluorine-containing compound; and heating the substrate at a temperature between 100° C. to 200° C.

摘要翻译： 本公开涉及集成电路制造，并且更具体地涉及具有几乎没有纹波的隔离结构的电子器件。 一种用于制造隔离结构的示例性方法，包括：在衬底的顶表面上形成衬垫氧化物层; 在所述衬垫氧化物层中形成开口，暴露所述衬底的一部分; 蚀刻衬底的暴露部分，在衬底中形成沟槽; 用绝缘体填充沟槽; 将衬垫氧化物层的表面和绝缘体的表面暴露于至少包含NH 3和含氟化合物的蒸汽混合物; 并在100℃至200℃的温度下加热基材。