公开(公告)号：US07659573B2

公开(公告)日：2010-02-09

申请号：US11833019

申请日：2007-08-02

Applicant: Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

Inventor： Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

IPC: H01L29/76

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66651

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区，形成在凹陷区的内表面上的凹陷沟道，其形成在源区和漏区之间的半导体衬底上， 掺杂掺杂物的外延半导体膜。 半导体器件还包括形成在凹槽上的栅极绝缘膜，以及填充凹陷区并形成在栅极绝缘膜上的栅电极。

公开(公告)号：US5903097A

公开(公告)日：1999-05-11

申请号：US998785

申请日：1997-12-29

Applicant: Yong-kyu Lee

Inventor： Yong-kyu Lee

IPC: H01J9/24 ,  H01J9/26 ,  H01J31/15 ,  H01J1/62

CPC classification number: H01J9/261

Abstract: A method of manufacturing a side glass for a vacuum fluorescent display is provided wherein a glass is cut to a predetermined length in accordance with the size of the vacuum fluorescent display. The glass is then bent to coincide two ends of the glass in accordance with the shape of the vacuum fluorescent display, and the two ends of the glass are adhered to one another. A sealing frit is applied on the upper side of the glass, and is plasticized and cured.

Abstract translation: 提供一种制造用于真空荧光显示器的侧玻璃的方法，其中根据真空荧光显示器的尺寸将玻璃切割成预定长度。 然后根据真空荧光显示器的形状将玻璃弯曲以使玻璃的两端重合，玻璃的两端彼此粘合。 将密封玻璃料施加在玻璃的上侧，并且被塑化和固化。

公开(公告)号：US20080035962A1

公开(公告)日：2008-02-14

申请号：US11833019

申请日：2007-08-02

Applicant: Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

Inventor： Young-ho Kim ,  Yong-kyu Lee ,  Myung-jo Chun

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/78 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66651

Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions formed on the semiconductor substrate, a recess channel that is formed on the inner surface of a recess region, which is formed on the semiconductor substrate between the source and drain regions, and in an epitaxial semiconductor film in which dopants are doped. The semiconductor device further includes a gate insulating film formed on the recess channel, and a gate electrode that fills the recess region and is formed on the gate insulating film.

Abstract translation: 半导体器件包括半导体衬底，形成在半导体衬底上的源极和漏极区，形成在凹陷区的内表面上的凹陷沟道，其形成在源区和漏区之间的半导体衬底上， 掺杂掺杂物的外延半导体膜。 半导体器件还包括形成在凹槽上的栅极绝缘膜，以及填充凹陷区并形成在栅极绝缘膜上的栅电极。

公开(公告)号：US20070267684A1

公开(公告)日：2007-11-22

申请号：US11804329

申请日：2007-05-17

Applicant: Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

Inventor： Hee-seog Jeon ,  Jeong-uk Han ,  Hyun-khe Yoo ,  Yong-kyu Lee

IPC: H01L29/788

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile memory integrated circuit device and a method fabricating the same are disclosed. The non-volatile memory integrated circuit device includes a semiconductor substrate, word and select lines, and a floating junction region, a bit line junction region and a common source region. The semiconductor substrate has a plurality of substantially rectangular field regions, and the short and long sides of each substantially rectangular field region are parallel to the row and column directions of a matrix, respectively. The word lines and select lines extend parallel to the row direction on the semiconductor substrate, the word lines crossing a plurality of substantially rectangular field regions disposed in the row direction, and the select lines partially overlapping substantially rectangular field regions arranged in the row direction of the matrix, such that the parts of the long sides of the substantially field regions and the short sides of the substantially rectangular field regions are located below the select lines. The floating junction region is formed within the semiconductor substrate between the word lines and the select lines, the bit line junction region is formed opposite the floating junction region, and the common source region is formed opposite the floating junction region.

Abstract translation: 公开了一种非易失性存储器集成电路器件及其制造方法。 非易失性存储器集成电路器件包括半导体衬底，字和选择线，以及浮置结区域，位线接合区域和公共源极区域。 半导体衬底具有多个基本上矩形的场区域，并且每个大致矩形场区域的短边和长边分别平行于矩阵的行和列方向。 字线和选择线在半导体衬底上平行于行方向延伸，字线与沿行方向设置的多个基本上矩形的场区交叉，并且选择线部分地重叠大致矩形的场区域 矩阵，使得基本上场区域的长边的部分和基本上矩形的场区域的短边位于选择线下方。 在半导体衬底之间，在字线和选择线之间形成浮点结区，与浮置结区相对地形成位线结区域，并且与浮接区相对地形成公共源极区。

公开(公告)号：US07005349B2

公开(公告)日：2006-02-28

申请号：US10781761

申请日：2004-02-20

Applicant: Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

Inventor： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: A method of manufacturing a twin-ONO-type SONOS memory using a reverse self-alignment process, wherein an ONO dielectric layer is formed under a gate and physically separated into two portions using a reverse self-alignment process irrespective of photolithographic limits. To facilitate the reverse self-alignment, a buffer layer and spacers for defining the width of the ONO dielectric layer are adopted. Thus, the dispersion of trapped charges during programming and erasing can be appropriately adjusted, thus improving the characteristics of the SONOS. The present invention prevents the redistribution of charges in time after the programming and erasing operations.

Abstract translation: 使用反向自对准工艺制造双ONO型SONOS存储器的方法，其中在栅极下形成ONO电介质层，并且使用反向自对准工艺物理地分离成两部分，而与光刻极限无关。 为了促进反向自对准，采用用于限定ONO介电层宽度的缓冲层和间隔物。 因此，可以适当地调整编程和擦除期间的捕获电荷的分散，从而改善SONOS的特性。 本发明防止在编程和擦除操作之后的时间内重新分配电荷。

公开(公告)号：US09583534B2

公开(公告)日：2017-02-28

申请号：US14795882

申请日：2015-07-09

Applicant: Choong-jae Lee ,  Hong-kook Min ,  Bo-young Seo ,  Aliaksei Ivaniukovich ,  Yong-kyu Lee

Inventor： Choong-jae Lee ,  Hong-kook Min ,  Bo-young Seo ,  Aliaksei Ivaniukovich ,  Yong-kyu Lee

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/228 ,  H01L29/1045 ,  H01L29/7833 ,  H01L29/7835 ,  H01L43/08

Abstract: A semiconductor device comprises a magneto-resistive device capable of performing multiple functions with low power. The semiconductor device comprises a cell transistor in which a first impurity region and a second impurity region are respectively arranged on both sides of a channel region in a channel direction, a source line connected to the first impurity region of the cell transistor, and the magneto-resistive device connected to the second impurity region of the cell transistor. The first impurity region and the second impurity region are asymmetrical about a center of the cell transistor in the channel direction with respect to at least one of a shape and an impurity concentration distribution.

Abstract translation: 半导体器件包括能够以低功率执行多个功能的磁阻器件。 半导体器件包括单元晶体管，其中第一杂质区域和第二杂质区域分别布置在沟道方向上的沟道区域的两侧，连接到单元晶体管的第一杂质区域的源极线和磁体 电阻器件连接到单元晶体管的第二杂质区域。 相对于形状和杂质浓度分布中的至少一种，第一杂质区域和第二杂质区域围绕单元晶体管的沟道方向的中心不对称。

公开(公告)号：US07652322B2

公开(公告)日：2010-01-26

申请号：US12014262

申请日：2008-01-15

Applicant: Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

Inventor： Byung-yong Choi ,  Chang-woo Oh ,  Dong-gun Park ,  Dong-won Kim ,  Yong-kyu Lee

IPC: H01L29/788

CPC classification number: H01L29/66825 ,  H01L29/42324 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract translation: 在能够在控制栅极和存储节点（浮动栅极）之间保持增强的电场并且具有减小的单元尺寸的闪存器件以及制造闪存器件的方法中，闪速存储器件包括半导体衬底 具有一对漏极区域和形成在所述一对漏极区域之间的源极区域，每个形成在所述源极区域和每个所述漏极区域之间的所述半导体衬底上的一对间隔物形状的控制栅极，以及形成在所述漏极区域中的存储节点 控制栅极和半导体衬底之间的区域。 每个控制栅极的底表面包括与半导体衬底重叠的第一区域和与存储节点重叠的第二区域。 一对间隔物控制栅极围绕源极区域彼此大致对称。

公开(公告)号：US07439574B2

公开(公告)日：2008-10-21

申请号：US10460673

申请日：2003-06-13

Applicant: Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

Inventor： Chung-woo Kim ,  Byung-gook Park ,  Jong-duk Lee ,  Yong-kyu Lee

IPC: H01L21/336

CPC classification number: H01L29/7926 ,  G11C11/5628 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/7923

Abstract: Provided are a silicon/oxide/nitride/oxide/silicon (SONOS) memory, a fabricating method thereof, and a memory programming method. The SONOS memory includes a substrate; a first insulating layer stacked on the substrate; a semiconductor layer, which is patterned on the first insulating layer in a predetermined shape, including source and drain electrodes separated by a predetermined interval; a second insulating layer located on the semiconductor layer between the source and drain electrodes; a memory layer, which is deposited on sides of a portion of the semiconductor layer between the source and drain electrodes and on sides and an upper surface of the second insulating layer, including electron transferring channels and an electron storing layer; and a gate electrode, which is deposited on a surface of the memory layer, for controlling transfer of electrons in the memory layer. The programming method may provide a large capacity, stable, multi-level memory.

Abstract translation: 提供了硅/氧化物/氮化物/氧化物/硅（SONOS）存储器，其制造方法和存储器编程方法。 SONOS存储器包括基板; 堆叠在所述基板上的第一绝缘层; 半导体层，其在预定形状的第一绝缘层上图案化，包括以预定间隔隔开的源极和漏极; 位于源极和漏极之间的半导体层上的第二绝缘层; 存储层，其沉积在源极和漏极之间的半导体层的一部分的侧面上，并且沉积在包括电子传输沟道和电子存储层的第二绝缘层的侧面和上表面上; 以及沉积在存储层的表面上用于控制存储层中电子转移的栅电极。 编程方法可以提供大容量，稳定的多级存储器。

公开(公告)号：US20060086953A1

公开(公告)日：2006-04-27

申请号：US11296397

申请日：2005-12-08

Applicant: Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

Inventor： Yong-kyu Lee ,  Jeong-uk Han ,  Sung-taeg Kang ,  Jong-duk Lee ,  Byung-gook Park

IPC: H01L29/76 ,  H01L29/745

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: A twin-ONO-type SONOS memory includes a semiconductor substrate having a source region, a drain region and a channel region between the source and drain regions, twin silicon oxide-silicon nitride-silicon oxide (ONO) dielectric layers, a first ONO dielectric layer being on the channel region and the source region and as second ONO dielectric layer being on the channel region and the drain region, and a control gate on the channel region, between the twin ONO dielectric layers, the twin ONO dielectric layers extending along at least lower lateral sides of the control gate adjacent the channel region, wherein the twin ONO dielectric layers extend towards the source and drain regions further than the control gate.

公开(公告)号：US09691459B2

公开(公告)日：2017-06-27

申请号：US15249845

申请日：2016-08-29

Applicant: Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik Kim

Inventor： Bo-young Seo ,  Suk-soo Pyo ,  Gwan-hyeob Koh ,  Yong-kyu Lee ,  Dae-shik Kim

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C7/14 ,  G11C11/1673 ,  G11C13/004 ,  G11C29/028 ,  G11C29/50008 ,  G11C2013/0054 ,  G11C2029/4402

Abstract: A semiconductor memory device includes a shorted variable resistor element in a memory cell. The semiconductor memory device includes main cells and reference cells each including a cell transistor and a variable resistor element. The variable resistor element of the reference cell is shorted by applying a breakdown voltage of a magnetic tunnel junction (MTJ) element, connection in parallel to a conductive via element, connection to a reference bit line at a node between the cell transistor and the variable resistor element, or replacement of the variable resistor element with the conductive via element. A sense amplifier increases a sensing margin of the main cell by detecting and amplifying a current flowing in a bit line of the main cell and a current flowing in the reference bit line to which a reference resistor is connected.