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    MULTI-LEVEL MEMORY DEVICES AND METHODS OF OPERATING THE SAME
    5.
    发明申请
    MULTI-LEVEL MEMORY DEVICES AND METHODS OF OPERATING THE SAME 有权
    多级存储器件及其操作方法

    公开(公告)号：US20120236627A1

    公开(公告)日：2012-09-20

    申请号：US13487463

    申请日：2012-06-04

    申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

    发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C11/56 ,  G11C13/0004

    摘要： The present invention provides a multi-level memory device and method of operating the same. The device comprises a memory structure in which a distribution density of resistance levels around its minimum value is higher than that around its maximum value.

    摘要翻译： 本发明提供了一种多级存储装置及其操作方法。 该装置包括存储器结构，其中电阻值在其最小值附近的分布密度高于围绕其最大值的分布密度。

    Methods of fabricating semiconductor devices with scalable two transistor memory cells
    7.
    发明授权
    Methods of fabricating semiconductor devices with scalable two transistor memory cells 失效
    用可扩展的双晶体管存储单元制造半导体器件的方法

    公开(公告)号：US07112492B2

    公开(公告)日：2006-09-26

    申请号：US11040229

    申请日：2005-01-21

    申请人： Su-Jin Ahn ,  Gwan-Hyeob Koh ,  Hyoung-Joon Kim

    发明人： Su-Jin Ahn ,  Gwan-Hyeob Koh ,  Hyoung-Joon Kim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11543 ,  H01L29/42324 ,  H01L29/7881

    摘要： Semiconductor devices having scalable two transistor memory cells, and methods of fabricating the same, are disclosed. The semiconductor devices include a semiconductor substrate having first, second and third isolation layers thereon. The first and second isolation layers are spaced apart to define a first active region therebetween, and the second and third isolation layers are likewise spaced apart to form a second active region therebetween. A cell gate is provided on each active region that includes a gate dielectric layer, a storage node, a multiple tunnel junction barrier and a source layer that are sequentially stacked. The device also includes first and second control lines that surround at least a portion of each sidewall of the cell gates. A dielectric layer may be interposed between the sidewalls of the cell gates and the control line that surrounds it. A data line connects to the cell gates.

    摘要翻译： 公开了具有可伸缩的双晶体管存储单元的半导体器件及其制造方法。 半导体器件包括其上具有第一，第二和第三隔离层的半导体衬底。 第一和第二隔离层间隔开以限定它们之间的第一有源区，并且第二隔离层和第三隔离层同样隔开以在它们之间形成第二有源区。 在每个有源区域上提供一个单元栅极，该栅极电介质层，存储节点，多个隧道结屏障和源层依次堆叠。 该装置还包括围绕电池栅极的每个侧壁的至少一部分的第一和第二控制线。 电介质层可以插在电池栅极的侧壁和围绕它的控制线之间。 数据线连接到单元门。

    Method of fabricating MOS transistors
    8.
    发明授权
    Method of fabricating MOS transistors 有权
    制造MOS晶体管的方法

    公开(公告)号：US06753227B2

    公开(公告)日：2004-06-22

    申请号：US10437881

    申请日：2003-05-13

    申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

    发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Ki-Nam Kim

    IPC分类号： H01L21336

    CPC分类号： H01L21/823807 ,  H01L21/28061 ,  H01L21/823892 ,  H01L29/4933

    摘要： A method of fabricating a MOS transistor is provided. According to the method, a rapid thermal anneal is applied to a semiconductor substrate having active regions doped with well impurity ions and channel impurity ions. Thus, during implantation of the well and the channel impurity ions, crystalline defects resulting from the implantation can be cured by the rapid thermal anneal.

    摘要翻译： 提供一种制造MOS晶体管的方法。 根据该方法，将快速热退火应用于具有掺杂有良好杂质离子和沟道杂质离子的有源区的半导体衬底。 因此，在注入阱和通道杂质离子期间，通过快速热退火可以固化由植入产生的结晶缺陷。

    Method for fabricating MOS transistor
    9.
    发明授权
    Method for fabricating MOS transistor 失效
    制造MOS晶体管的方法

    公开(公告)号：US06335233B1

    公开(公告)日：2002-01-01

    申请号：US09347822

    申请日：1999-07-02

    申请人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Mi-Hyang Lee ,  Dae-Won Ha

    发明人： Chang-Hyun Cho ,  Gwan-Hyeob Koh ,  Mi-Hyang Lee ,  Dae-Won Ha

    IPC分类号： H01L218238

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/7833

    摘要： A first conductive impurity ion is implanted into a semiconductor substrate to form a well area on which a gate electrode is formed. A first non-conductive impurity is implanted into the well area on both sides of the gate electrode to control a substrate defect therein and to form a first precipitate area to a first depth. A second conductive impurity ion is implanted into the well area on both sides of the gate electrode, so that a source/drain area is formed to a second depth being relatively shallower than the first depth. A second non-conductive impurity is implanted into the source/drain area so as to control a substrate defect therein and to form a second precipitate area. As a result, substrate defects such as dislocation, extended defect, and stacking fault are isolated from a P-N junction area, thereby forming a stable P-N junction.

    摘要翻译： 将第一导电杂质离子注入到半导体衬底中以形成其上形成栅电极的阱区。 将第一非导电杂质注入到栅极两侧的阱区中以控制其中的衬底缺陷并形成第一深度的第一沉淀区。 将第二导电杂质离子注入到栅极两侧的阱区中，使得源/漏区形成为比第一深度相对浅的第二深度。 将第二非导电杂质注入源/漏区，以便控制其中的衬底缺陷并形成第二沉淀区。 结果，从P-N结区域隔离诸如位错，延伸缺陷和堆垛层错的基板缺陷，从而形成稳定的P-N结。