公开(公告)号：US20090098719A1

公开(公告)日：2009-04-16

申请号：US12188676

申请日：2008-08-08

申请人： Yoshinori MATSUNO ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Shozo Shikama ,  Naoki Yutani

发明人： Yoshinori MATSUNO ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Shozo Shikama ,  Naoki Yutani

IPC分类号： H01L21/04

CPC分类号： H01L21/0495 ,  H01L29/6606

摘要： An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer.

摘要翻译： 本发明的目的是提供一种制造具有恒定特性并减小正向特性变化的碳化硅半导体器件的方法。 根据本发明的制造碳化硅半导体器件的方法包括以下步骤：（a）制备碳化硅衬底; （b）在所述碳化硅衬底的第一主表面上形成外延层; （c）在外延层上形成保护膜; （d）在所述碳化硅衬底的第二主表面上形成第一金属层; （e）在预定温度下对所述碳化硅衬底进行热处理以在所述第一金属层和所述碳化硅衬底的所述第二主表面之间形成欧姆结; （f）去除保护膜; （g）在所述外延层上形成第二金属层; 和（h）在400℃至600℃的温度下对所述碳化硅衬底进行热处理以在所述第二金属层和所述外延层之间形成所需特性的肖特基结。

公开(公告)号：US08377811B2

公开(公告)日：2013-02-19

申请号：US12188676

申请日：2008-08-08

申请人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Shozo Shikama ,  Naoki Yutani

发明人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Shozo Shikama ,  Naoki Yutani

IPC分类号： H01L21/28

CPC分类号： H01L21/0495 ,  H01L29/6606

摘要： An object of the invention is to provide a method for manufacturing a silicon carbide semiconductor device having constant characteristics with reduced variations in forward characteristics. The method for manufacturing the silicon carbide semiconductor device according to the invention includes the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on a first main surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on a second main surface of the silicon carbide substrate; (e) applying heat treatment to the silicon carbide substrate at a predetermined temperature to form an ohmic junction between the first metal layer and the second main surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a second metal layer on the epitaxial layer; and (h) applying heat treatment to the silicon carbide substrate at a temperature from 400° C. to 600° C. to form a Schottky junction of desired characteristics between the second metal layer and the epitaxial layer.

摘要翻译： 本发明的目的是提供一种制造具有恒定特性并减小正向特性变化的碳化硅半导体器件的方法。 根据本发明的制造碳化硅半导体器件的方法包括以下步骤：（a）制备碳化硅衬底; （b）在所述碳化硅衬底的第一主表面上形成外延层; （c）在所述外延层上形成保护膜; （d）在所述碳化硅衬底的第二主表面上形成第一金属层; （e）在预定温度下对所述碳化硅衬底进行热处理以在所述第一金属层和所述碳化硅衬底的所述第二主表面之间形成欧姆结; （f）去除保护膜; （g）在所述外延层上形成第二金属层; 和（h）在400℃至600℃的温度下对所述碳化硅衬底进行热处理以在所述第二金属层和所述外延层之间形成所需特性的肖特基结。

公开(公告)号：US08569123B2

公开(公告)日：2013-10-29

申请号：US13258941

申请日：2009-09-01

申请人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

发明人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

IPC分类号： H01L21/338

CPC分类号： H01L21/046 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

摘要翻译： 本发明的目的是提供一种用于制造碳化硅半导体器件的方法，其中可以缩短去除牺牲氧化膜所需的时间，并且可以降低对碳化硅层的表面的损坏。 制造碳化硅半导体器件的方法包括：（a）对碳化硅层进行离子注入; （b）对离子注入碳化硅层2进行激活退火; （c）通过干蚀刻去除已经进行了活化退火的碳化硅层2的表面层; （d）通过对其进行牺牲氧化，在已经进行了干蚀刻的碳化硅层的表面层上形成牺牲氧化膜; 和（e）通过湿蚀刻去除牺牲氧化膜。

公开(公告)号：US20120028453A1

公开(公告)日：2012-02-02

申请号：US13258941

申请日：2009-09-01

申请人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

发明人： Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Naoki Yutani ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Shozo Shikama

IPC分类号： H01L21/265

CPC分类号： H01L21/046 ,  H01L21/0495 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

摘要： An object is to provide a method for manufacturing a silicon carbide semiconductor device in which a time required for removing a sacrificial oxide film can be shortened and damage to a surface of the silicon carbide layer can be reduced. The method for manufacturing a silicon carbide semiconductor device includes: (a) performing ion implantation to a silicon carbide layer; (b) performing activation annealing to the ion-implanted silicon carbide layer 2; (c) removing a surface layer of the silicon carbide layer 2, to which the activation annealing has been performed, by dry etching; (d) forming a sacrificial oxide film on a surface layer of the silicon carbide layer, to which the dry etching has been performed, by performing sacrificial oxidation thereto; and (e) removing the sacrificial oxide film by wet etching.

摘要翻译： 本发明的目的是提供一种用于制造碳化硅半导体器件的方法，其中可以缩短去除牺牲氧化膜所需的时间，并且可以降低对碳化硅层的表面的损坏。 制造碳化硅半导体器件的方法包括：（a）对碳化硅层进行离子注入; （b）对离子注入碳化硅层2进行激活退火; （c）通过干蚀刻去除已经进行了活化退火的碳化硅层2的表面层; （d）通过对其进行牺牲氧化，在已经进行了干蚀刻的碳化硅层的表面层上形成牺牲氧化膜; 和（e）通过湿蚀刻去除牺牲氧化膜。

公开(公告)号：US20110001209A1

公开(公告)日：2011-01-06

申请号：US12867283

申请日：2009-03-12

申请人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

发明人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

IPC分类号： H01L29/47

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− typesemiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.

摘要翻译： 在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质 通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。 半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成由形成在所述GR层之外的围绕所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

公开(公告)号：US08304901B2

公开(公告)日：2012-11-06

申请号：US12867283

申请日：2009-03-12

申请人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

发明人： Hiroshi Watanabe ,  Naoki Yutani ,  Kenichi Ohtsuka ,  Kenichi Kuroda ,  Masayuki Imaizumi ,  Yoshinori Matsuno

IPC分类号： H01L23/48

CPC分类号： H01L29/872 ,  H01L21/0495 ,  H01L24/05 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L2924/12032 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00

摘要： In a termination structure in which a JTE layer is provided, a level or defect existing at an interface between a semiconductor layer and an insulating film, or a minute amount of adventitious impurities that infiltrate into the semiconductor interface from the insulating film or from an outside through the insulating film becomes a source or a breakdown point of a leakage current, which deteriorates a breakdown voltage. A semiconductor device includes: an n− type semiconductor layer formed on an n+ type semiconductor substrate; a first electrode that is formed on the n− type semiconductor layer and functions as a Schottky electrode; a GR layer that is a first p type semiconductor layer formed on a surface of the n− type semiconductor layer below an end of the first electrode and a perimeter thereof; a JTE layer that is formed of a second p type semiconductor layer formed on a bottom and a lateral surface of a groove arranged in a ring shape around the GR layer apart from the GR layer, in a surface of the n− type semiconductor layer; an insulating film provided so as to cover the GR layer and the JTE layer; and a second electrode that is an Ohmic electrode formed below a rear surface of the n+ type semiconductor substrate.

摘要翻译： 在提供JTE层的端接结构中，存在于半导体层和绝缘膜之间的界面处的水平或缺陷，或从绝缘膜或外部渗透到半导体界面的少量不定性杂质 通过绝缘膜成为漏电流的源极或击穿点，这会降低击穿电压。 半导体器件包括：形成在n +型半导体衬底上的n型半导体层; 形成在n型半导体层上并用作肖特基电极的第一电极; GR层，其是形成在所述第一电极的端部下方的所述n型半导体层的表面上的第一p型半导体层及其周边; 在所述n型半导体层的表面中形成有由形成在所述GR层之外的与所述GR层相邻的所述GR层的环状的槽的底部和侧面上形成的第二p型半导体层的JTE层; 设置为覆盖GR层和JTE层的绝缘膜; 以及形成在n +型半导体衬底的后表面下方的欧姆电极的第二电极。

公开(公告)号：US09059193B2

公开(公告)日：2015-06-16

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/15 ,  H01L29/66 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02 ,  H01L29/10 ,  H01L29/16 ,  H01L29/872 ,  H01L21/04 ,  H01L29/78

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US20120241766A1

公开(公告)日：2012-09-27

申请号：US13514201

申请日：2010-12-27

申请人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

发明人： Kenichi Ohtsuka ,  Kenichi Kuroda ,  Hiroshi Watanabe ,  Naoki Yutani ,  Hiroaki Sumitani

IPC分类号： H01L29/167

CPC分类号： H01L29/66068 ,  C30B23/02 ,  C30B25/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02447 ,  H01L21/02496 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/0495 ,  H01L29/107 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/7802 ,  H01L29/7827 ,  H01L29/872

摘要： A silicon carbide semiconductor element, including: i) an n-type silicon carbide substrate doped with a dopant, such as nitrogen, at a concentration C, wherein the substrate has a lattice constant that decreases with doping; ii) an n-type silicon carbide epitaxially-grown layer doped with the dopant, but at a smaller concentration than the substrate; and iii) an n-type buffer layer doped with the dopant, and arranged between the substrate and the epitaxially-grown layer, wherein the buffer layer has a multilayer structure in which two or more layers having the same thickness are laminated, and is configured such that, based on a number of layers (N) in the multilayer structure, a doping concentration of a K-th layer from a silicon carbide epitaxially-grown layer side is C·K/(N+1).

摘要翻译： 一种碳化硅半导体元件，包括：i）以浓度C掺杂有诸如氮的掺杂剂的n型碳化硅衬底，其中所述衬底具有随着掺杂而降低的晶格常数; ii）掺杂有掺杂剂但以比衬底更小的浓度的n型碳化硅外延生长层; 并且iii）掺杂有掺杂剂的n型缓冲层，并且布置在所述衬底和所述外延生长层之间，其中所述缓冲层具有其中层叠具有相同厚度的两层或更多层的多层结构，并且被配置 使得基于多层结构中的多个层（N），来自碳化硅外延生长层的第K层的掺杂浓度为C·K /（N + 1）。

公开(公告)号：US07564072B2

公开(公告)日：2009-07-21

申请号：US11142322

申请日：2005-06-02

申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

IPC分类号： H01L29/74

CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/872 ,  Y10S388/917

摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.

摘要翻译： 半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成 比第一个p型区域。 第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。 第一p型区域的表面杂质浓度范围为1.8×1013〜4×1013cm-2，第二p型区域的表面杂质浓度为1×10 13〜2.5×10 13 cm -2。

公开(公告)号：US20090134404A1

公开(公告)日：2009-05-28

申请号：US12066366

申请日：2006-04-24

申请人： Hiroshi Sugimoto ,  Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Noboru Mikami ,  Kenichi Kuroda

发明人： Hiroshi Sugimoto ,  Yoshinori Matsuno ,  Kenichi Ohtsuka ,  Noboru Mikami ,  Kenichi Kuroda

IPC分类号： H01L29/24

CPC分类号： H01L29/8611 ,  H01L21/0445 ,  H01L29/045 ,  H01L29/0684 ,  H01L29/1608 ,  H01L29/6606

摘要： On a major surface of an n-type silicon carbide inclined substrate (2) is formed an n-type voltage-blocking layer (3) made of silicon carbide by means of epitaxial growth. On the n-type voltage-blocking layer (3) is formed a p-type silicon carbide region (4) rectangular when viewed from above. On the surface of the p-type silicon carbide region (4) is formed a p-type contact electrode (5). In the p-type silicon carbide region (4), the periphery of the p-type silicon carbide region (4) that is parallel with a (11-20) plane (14a) of the silicon carbide crystal, which is liable to cause avalanche breakdown, is located on the short side. In this manner, the dielectric strength of a silicon carbide semiconductor device can be improved.

摘要翻译： 在n型碳化硅倾斜衬底（2）的主表面上通过外延生长形成由碳化硅制成的n型压阻层（3）。 在从上方观察时，在n型电压阻挡层（3）上形成矩形的p型碳化硅区域（4）。 在p型碳化硅区域（4）的表面上形成p型接触电极（5）。 在p型碳化硅区域（4）中，与碳化硅晶体的（11-20）面（14a）平行的p型碳化硅区域（4）的周边易于引起 雪崩破裂，位于短边。 以这种方式，可以提高碳化硅半导体器件的介电强度。