公开(公告)号：US5397743A

公开(公告)日：1995-03-14

申请号：US33043

申请日：1993-03-18

申请人： Young K. Jun ,  Chang J. Lee

发明人： Young K. Jun ,  Chang J. Lee

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L23/522 ,  H01L21/44

CPC分类号： H01L21/76885 ,  H01L21/768 ,  H01L21/7684 ,  H01L23/5221 ,  H01L2924/0002

摘要： A method of making a semiconductor device capable of simplifying the overall manufacturing processes and carrying out the reliable interconnections between wires. The method includes forming a first insulator over a semiconductor substrate, forming a first conductor over the first insulator and then patterning the first conductor to form a plurality of first wires, forming a second insulator over the entire exposed surface and then removing a portion of the second insulator disposed over the surface of a selector first wire to form a contact hole, forming a second conductor over the entire exposed surface and then patterning the second conductor to form an interconnection wire over the contact hole, forming a third insulator having uniform thickness and a fourth insulator having the smoothing surface in this order, etching back the third insulator and the fourth insulator, until the surface of the interconnection wire is exposed, and forming a third conductor having an uniform thickness over the entire exposed surface and the then patterning the third conductor to form a second wire to be connected to the selected first wire through the interconnection wire.

摘要翻译： 制造半导体器件的方法，该半导体器件能够简化整个制造过程并且执行电线之间的可靠互连。 该方法包括在半导体衬底上形成第一绝缘体，在第一绝缘体上形成第一导体，然后对第一导体进行构图以形成多个第一导线，在整个暴露表面上形成第二绝缘体，然后去除一部分 第二绝缘体设置在选择器第一线的表面上以形成接触孔，在整个暴露表面上形成第二导体，然后构图第二导体，以在接触孔上形成互连线，形成具有均匀厚度的第三绝缘体， 具有平滑表面的第四绝缘体，蚀刻第三绝缘体和第四绝缘体，直到互连线的表面露出，并且在整个暴露表面上形成具有均匀厚度的第三导体，然后图案化 以形成通过互连件连接到所选择的第一导线的第二导线 电线。

公开(公告)号：US5393373A

公开(公告)日：1995-02-28

申请号：US135197

申请日：1993-10-12

申请人： Young K. Jun ,  Sa K. Ra ,  Dong W. Kim ,  Hyun H. Seo ,  Sung C. Kim ,  Jun K. Kim

发明人： Young K. Jun ,  Sa K. Ra ,  Dong W. Kim ,  Hyun H. Seo ,  Sung C. Kim ,  Jun K. Kim

IPC分类号： H01L21/02 ,  H01L21/033 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/306 ,  B44C1/22

CPC分类号： H01L27/10817 ,  H01L21/0337 ,  H01L27/10852 ,  H01L28/92 ,  Y10S438/942

摘要： Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.

摘要翻译： 超精细图案化和制造半导体器件的方法。 根据本发明的步骤包括在待蚀刻的层上涂覆具有山丘和谷的半球粒子层，该半球粒子层的蚀刻选择性高于第一层的蚀刻选择性，将半球粒子层的谷部填充到半球粒子层的谷部 第二层具有比半球颗粒层的蚀刻选择性更高的蚀刻选择性，并且通过使用第二层作为掩模蚀刻半球粒子层的山丘以暴露第一层，并蚀刻第一层。 由于半球颗粒层具有交替的山丘和山谷，可以实现约0.1μm的超精细图案化。 由于可以控制半球层的平均尺寸和丘陵和山谷的密度，因此也可以控制图案尺寸。 在将本发明应用于半导体存储器元件的电容器的情况下，可以根据多晶硅层的蚀刻回深度来增加电容器节点表面积。

公开(公告)号：US5346847A

公开(公告)日：1994-09-13

申请号：US131707

申请日：1993-10-05

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10808 ,  Y10S257/905

摘要： The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

摘要翻译： 本发明涉及一种半导体存储器件，其中在位线的上部和下部形成用作位线的位线环，并且存储节点形成为与形成的所述位线在相同的方向上重叠 垂直于字线提高整合度。 因此，可以增加电容器面积而不增加单位电池的面积，以提高半导体存储器件的集成度，并且可以避免有源区域的弯曲部分的产生以减小失真。

公开(公告)号：US5459094A

公开(公告)日：1995-10-17

申请号：US193703

申请日：1994-02-08

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： A semiconductor memory device including a plurality of memory cells arranged in a matrix manner, each of the memory cells including a transfer transistor constituted by a gate electrode, a gate insulating film, a source region and a drain region, and a charge storage capacitor constituted by a storage node, a dielectric film and a plate electrode, the storage node of the charge storage capacitor including a cylindrical lower electrode formed above the transfer transistor via an insulating layer formed on the transfer transistor and connected to one of the source region and the drain region of the transfer transistor, and a cover type upper electrode formed on the lower electrode and connected with the lower electrode. By the composite structure of the capacitor storage node including the lower structure having the cylinder shape and the cover type upper structure connected with the lower structure, it is possible to utilize efficiently a three-dimensional space structure and thereby achieve an increase in capacitance.

摘要翻译： 一种半导体存储器件，包括以矩阵方式布置的多个存储单元，每个存储单元包括由栅极电极，栅极绝缘膜，源极区域和漏极区域构成的转移晶体管和构成的电荷存储电容器 通过存储节点，电介质膜和平板电极，电荷存储电容器的存储节点包括通过形成在转移晶体管上的绝缘层形成在转移晶体管上方的圆筒形下电极，并连接到源区和 漏区，以及形成在下电极上并与下电极连接的盖型上电极。 通过电容器存储节点的复合结构，包括具有圆筒形状的下部结构和与下部结构连接的盖型上部结构，可以有效地利用三维空间结构，从而实现电容的增加。

公开(公告)号：US5256591A

公开(公告)日：1993-10-26

申请号：US898209

申请日：1992-06-12

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L21/308 ,  H01L21/762 ,  H01L21/76

CPC分类号： H01L21/3086 ,  H01L21/76232

摘要： A method for forming an isolation region in a semiconductor device using a trench comprising the steps of forming a reaction restraining layer on a semiconductor substrate, removing a portion of the reaction restraining layer corresponding to a trench region for providing an isolation region, forming a reaction film on the entire exposed surface, heat treating the reaction film and the substrate, to form a reaction product film having a predetermined depth in a portion of the reaction film and a portion of the substrate corresponding to said trench region, etching and removing the reaction product film, to form a trench, forming an insulation film for the isolation region such that it fills sufficiently the trench, forming a surface smoothing insulation film on the insulation film for the isolation region, etching back both the insulation films such that their portions located above a predetermined height from the surface of the substrate are removed, and removing the remaining reaction restraining layer.

摘要翻译： 一种在使用沟槽的半导体器件中形成隔离区域的方法，包括以下步骤：在半导体衬底上形成反应抑制层，除去与用于提供隔离区域的沟槽区域对应的反应抑制层的一部分，形成反应 在整个曝光表面上进行热处理，对反应膜和基板进行热处理，以形成在反应膜的一部分中具有预定深度的反应产物膜和对应于所述沟槽区的一部分基板，蚀刻和除去反应 形成沟槽，形成用于隔离区域的绝缘膜，使得其充分填充沟槽，在用于隔离区域的绝缘膜上形成表面平滑绝缘膜，对两个绝缘膜进行回蚀以使它们的部分位于 从衬底的表面上方超过预定高度，并除去剩余的反应物 n限制层。

公开(公告)号：US5256587A

公开(公告)日：1993-10-26

申请号：US911594

申请日：1992-07-10

申请人： Young K. Jun ,  Sa K. Ra ,  Dong W. Kim ,  Hyun H. Seo ,  Sung C. Kim ,  Jun K. Kim

发明人： Young K. Jun ,  Sa K. Ra ,  Dong W. Kim ,  Hyun H. Seo ,  Sung C. Kim ,  Jun K. Kim

IPC分类号： G03F7/09 ,  H01L21/02 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/70

CPC分类号： H01L28/92 ,  G03F7/094 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/32139 ,  Y10S148/138 ,  Y10S438/947 ,  Y10S438/97

摘要： Methods of hyperfine patterning and manufacturing semiconductor devices. Steps in accordance with the present invention include coating a hemisphere particle layer having hills and valleys on a layer to be etched, the hemisphere particle layer having an etch selectivity higher than that of the first layer, filling the valleys of the hemisphere particle layer with a second layer having an etch selectivity higher than that of the hemisphere particle layer, and etching back the hills of the hemisphere particle layer to expose the first layer by using the second layer as a mask, and etching the first layer. By virtue of the hemisphere particle layer having alternating hills and valleys, it is possible to accomplish a hyperfine patterning of about 0.1 .mu.m. Since the mean size and the density of hills and valleys of the hemisphere layer can be controlled, the pattern size also can be controlled. Where the present invention is applied to capacitors of semiconductor memory elements, the capacitor node surface area can be increased, depending on the etched back depth of a polysilicon layer.

摘要翻译： 超精细图案化和制造半导体器件的方法。 根据本发明的步骤包括在待蚀刻的层上涂覆具有山丘和谷的半球粒子层，该半球粒子层的蚀刻选择性高于第一层的蚀刻选择性，将半球粒子层的谷部填充到半球粒子层的谷部 第二层具有比半球颗粒层的蚀刻选择性更高的蚀刻选择性，并且通过使用第二层作为掩模蚀刻半球粒子层的山丘以暴露第一层，并蚀刻第一层。 由于半球颗粒层具有交替的山丘和山谷，可以实现约0.1μm的超精细图案化。 由于可以控制半球层的平均尺寸和丘陵和山谷的密度，因此也可以控制图案尺寸。 在将本发明应用于半导体存储器元件的电容器的情况下，可以根据多晶硅层的蚀刻回深度来增加电容器节点表面积。

公开(公告)号：US5468677A

公开(公告)日：1995-11-21

申请号：US360602

申请日：1994-12-21

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L21/76 ,  H01L21/265 ,  H01L21/318 ,  H01L21/762

CPC分类号： H01L21/76216

摘要： An isolation structure of a semiconductor device including a channel stop diffusion region selectively formed on a portion of a single crystalline silicon substrate disposed beneath an edge of a field oxide film formed on the substrate, thereby capable of selectively increasing, irrespective of a pattern size of the field region, a channel ion concentration at an edge of a field region where the field region is connected to an active region and which region is a weak area serving to decrease a channel stop ion concentration at an interface between the field oxide film and the silicon substrate and to decrease a threshold voltage of a field transistor due to a small thickness thereof and thereby locally increasing the threshold voltage. By the local increase in threshold voltage, it is possible to prevent a degradation in insulating characteristic of the field transistor with a small pattern size.

摘要翻译： 一种半导体器件的隔离结构，包括：沟道阻挡扩散区，其选择性地形成在单晶硅衬底的一部分上，该单晶硅衬底设置在形成于衬底上的场氧化膜的边缘下方，从而能够有选择地增加，而不管图案尺寸如何 场区域，其中场区域连接到有源区域的场区域的边缘处的通道离子浓度，并且该区域是用于减小场氧化物膜和场区域之间的界面处的通道停止离子浓度的弱区域 并且由于其小的厚度而降低场晶体管的阈值电压，从而局部地增加阈值电压。 通过阈值电压的局部增加，可以防止具有小图案尺寸的场效应晶体管的绝缘特性的劣化。

公开(公告)号：US5362664A

公开(公告)日：1994-11-08

申请号：US190304

申请日：1994-02-02

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L28/87 ,  H01L27/10817

摘要： This invention relates to a method for fabricating a semiconductor memory device with a large capacitance, which comprises the steps of forming a gate insulating film, a gate electrode and a source and drain region on a semiconductor substrate, forming an interlayer and an etch stopper on the whole surface, etching selectively away the etch stopper and the interlayer to form an opening, forming a first conductive layer, a first insulating film and a second insulating film on the whole surface, etching selectively away the first and second insulating film, forming a side wall spacer of a third insulating film on the side of the first and second insulating film, forming a fourth insulating film on the whole surface, etching selectively away the fourth insulating film, removing the second insulating film and the side wall spacer, forming a second conductive layer on the whole surface, etching selectively away the second conductive layer and the first insulating film and the first conductive layer, removing the fourth insulating film and the first insulating film.

摘要翻译： 本发明涉及一种用于制造具有大电容的半导体存储器件的方法，其包括以下步骤：在半导体衬底上形成栅极绝缘膜，栅极电极和源极和漏极区域，形成中间层和蚀刻终止器 整个表面，选择性地蚀刻蚀刻停止层和中间层以形成开口，在整个表面上形成第一导电层，第一绝缘膜和第二绝缘膜，选择性地蚀刻掉第一和第二绝缘膜，形成 在第一绝缘膜和第二绝缘膜一侧的第三绝缘膜的侧壁间隔物，在整个表面上形成第四绝缘膜，选择性地蚀刻掉第四绝缘膜，去除第二绝缘膜和侧壁间隔物，形成 在整个表面上的第二导电层，选择性地去除第二导电层和第一绝缘膜和第一导电层 ve层，去除第四绝缘膜和第一绝缘膜。

公开(公告)号：US5336630A

公开(公告)日：1994-08-09

申请号：US975884

申请日：1992-11-13

申请人： Kwang H. Yun ,  Hee G. Lee ,  Seong J. Jang ,  Young K. Jun

发明人： Kwang H. Yun ,  Hee G. Lee ,  Seong J. Jang ,  Young K. Jun

IPC分类号： G03F7/20 ,  H01L21/027 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70

CPC分类号： H01L27/10844 ,  G03F7/70425 ,  H01L27/10817 ,  Y10S438/943

摘要： A method of making a semiconductor memory device wherein a storage node having a plurality of pillars, capable of increasing the storage node surface area and thus the cell capacitance. The storage node is formed by depositing a storage node polysilicon film to have a thickness of 5,000 .ANG. to 6,000 .ANG. over a semiconductor substrate, forming a photoresist pattern over the polysilicon film in a direct electron beam writing manner, and etching the polysilicon film up to a depth of 1,000 .ANG. from the upper surfaces of a gate and a bit line by using the photoresist pattern. The formed storage node has a plurality of uniformly spaced pillars. Alternatively, the storage node is formed by forming a smoothing insulating film over the semiconductor substrate depositing a storage node polysilicon film over the smoothing insulating film, primarily photo exposing the semiconductor substrate using a glass mask having phase shifters, secondarily photo exposing the semiconductor substrate under the condition of rotating 90.degree. the semiconductor substrate, to form a check-board photoresist pattern, and patterning the polysilicon film using the photoresist pattern as a mask. The formed storage node has a plurality of pillars arranged independently or intersectionally.

摘要翻译： 一种制造半导体存储器件的方法，其中具有多个柱的存储节点，其能够增加存储节点表面积，从而增加单元电容。 存储节点通过在半导体衬底上沉积厚度为5000至6000的存储节点多晶硅膜形成，以直接电子束写入方式在多晶硅膜上形成光致抗蚀剂图案，并将多晶硅膜蚀刻至 通过使用光致抗蚀剂图案，从栅极和位线的上表面的深度为1000安培。 形成的存储节点具有多个均匀间隔的柱。 或者，存储节点通过在半导体衬底上形成平滑绝缘膜形成，在平滑绝缘膜上沉积存储节点多晶硅膜，主要是使用具有移相器的玻璃掩模对半导体衬底进行曝光，其次将半导体衬底照射到 旋转90°半导体衬底的条件，以形成校准板光致抗蚀剂图案，并使用光致抗蚀剂图案作为掩模对多晶硅膜进行构图。 形成的存储节点具有独立或相互排列的多个支柱。

公开(公告)号：US5270561A

公开(公告)日：1993-12-14

申请号：US850676

申请日：1992-03-13

申请人： Young K. Jun

发明人： Young K. Jun

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01L29/78 ,  H01L29/92

CPC分类号： H01L27/10808 ,  Y10S257/905

摘要： The invention relates to a semiconductor memory device in which a bit line ring which functions as a bit line is formed at the upper and lower stage of the bit line and a storage node is formed to be overlapped in the same direction with said bit line formed perpendicularly to a word line to improve the integration degree.Therefore, a capacitor area can be increased without an increase of an area of the unit cell to improve the integration degree of a semiconductor memory device and the generation of the bent portion of the active region can be avoided to decrease the distortion.

摘要翻译： 本发明涉及一种半导体存储器件，其中在位线的上部和下部形成用作位线的位线环，并且存储节点形成为与形成的所述位线在相同的方向上重叠 垂直于字线提高整合度。 因此，可以增加电容器面积而不增加单位电池的面积，以提高半导体存储器件的集成度，并且可以避免有源区域的弯曲部分的产生以减小失真。