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    Interface Bus Combining
    1.
    发明公开
    Interface Bus Combining 审中-公开

    公开(公告)号：US20240241849A1

    公开(公告)日：2024-07-18

    申请号：US18420431

    申请日：2024-01-23

    Applicant: pSemi Corporation

    Inventor： Poojan Wagh ,  David A. Podsiadlo

    IPC: G06F13/40 ,  G06F9/30

    CPC classification number: G06F13/4027 ,  G06F9/30101

    Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

    Interface Bus Combining
    2.
    发明申请
    Interface Bus Combining 有权

    公开(公告)号：US20220405227A1

    公开(公告)日：2022-12-22

    申请号：US17354530

    申请日：2021-06-22

    Applicant: pSemi Corporation

    Inventor： Poojan Wagh ,  David A. Podsiadlo

    IPC: G06F13/40 ,  G06F9/30

    Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

    Standby Voltage Condition for Fast RF Amplifier Bias Recovery
    3.
    发明申请
    Standby Voltage Condition for Fast RF Amplifier Bias Recovery 有权

    公开(公告)号：US20210119583A1

    公开(公告)日：2021-04-22

    申请号：US17074070

    申请日：2020-10-19

    Applicant: pSemi Corporation

    Inventor： Poojan Wagh ,  Kashish Pal

    IPC: H03F1/02 ,  H03F1/56 ,  H03F3/193 ,  H03F1/22 ,  H03F1/30 ,  H03F3/189

    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

    Standby Voltage Condition for Fast RF Amplifier Bias Recovery
    4.
    发明申请
    Standby Voltage Condition for Fast RF Amplifier Bias Recovery 有权

    公开(公告)号：US20240405724A1

    公开(公告)日：2024-12-05

    申请号：US18656926

    申请日：2024-05-07

    Applicant: pSemi Corporation

    Inventor： Poojan Wagh ,  Kashish Pal

    IPC: H03F1/02 ,  H03F1/22 ,  H03F1/30 ,  H03F1/56 ,  H03F3/189 ,  H03F3/193

    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit standby current during operation in the standby mode while allowing a quick recovery to normal operating conditions of the amplifier. Biasing an input transistor of the stacked transistors can be obtained by using a replica stack circuit.

    Interface bus combining
    9.
    发明授权
    Interface bus combining 有权

    公开(公告)号：US11886228B2

    公开(公告)日：2024-01-30

    申请号：US17354530

    申请日：2021-06-22

    Applicant: pSemi Corporation

    Inventor： Poojan Wagh ,  David A. Podsiadlo

    IPC: G06F13/38 ,  G06F13/42 ,  G06F13/40 ,  G06F9/30

    CPC classification number: G06F13/4027 ,  G06F9/30101

    Abstract: Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

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