利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

966 条记录 (耗时 0.026 秒)

    STANDARD CELL DESIGN
    1.
    发明公开
    STANDARD CELL DESIGN 审中-公开

    公开(公告)号：US20240362392A1

    公开(公告)日：2024-10-31

    申请号：US18769843

    申请日：2024-07-11

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Shu-Wei Chung ,  Tung-Heng Hsieh ,  Chung-Hui Chen ,  Chung-Yi Lin

    IPC分类号： G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F111/20

    CPC分类号： G06F30/392 ,  G06F30/323 ,  G06F30/398 ,  G06F2111/20

    摘要： An analog standard cell is provided. An analog standard cell according to the present disclosure includes a first active region and a second active region extending along a first direction, and a plurality of conductive lines in a first metal layer over the first active region and the second active region. The plurality of conductive lines includes a first conductive line and a second conductive line disposed directly over the first active region, a third conductive line and a fourth conductive line disposed directly over the second active region, a middle conductive line disposed between the second conductive line and the third conductive line, a first power line spaced apart from the middle conductive line by the first conductive line and the second conductive line, and a second power line spaced apart from the middle conductive line by the third conductive line and the fourth conductive line.

    Systems and methods for integrated circuit layout
    3.
    发明授权
    Systems and methods for integrated circuit layout 有权

    公开(公告)号：US12131108B2

    公开(公告)日：2024-10-29

    申请号：US18518167

    申请日：2023-11-22

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Kenan Yu ,  Qingwen Deng

    IPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F111/20

    CPC分类号： G06F30/3312 ,  G06F30/327 ,  G06F30/392 ,  G06F30/394 ,  G06F2111/20

    摘要： A method for providing an IC design is disclosed. The method includes receiving and synthesizing a behavioral description of an IC design; generating, based on the synthesized behavioral description, a layout for the IC design; performing at least a timing analysis on the layout; accessing, based on the timing analysis, a first cell library including a plurality of transistor-based cells, each having one or more transistors and associated with a respective first delay value; accessing, based on the timing analysis, a second cell library including a plurality of non-transistor-based cells, each having no transistor and associated with a respective second delay value; and updating the layout by at least one of inserting one or more of the plurality of transistor-based cells or inserting one or more of the plurality of non-transistor-based cells.

    Method of making cell regions of integrated circuits
    5.
    发明授权
    Method of making cell regions of integrated circuits 有权

    公开(公告)号：US12124785B2

    公开(公告)日：2024-10-22

    申请号：US18448115

    申请日：2023-08-10

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Jia-Hong Gao ,  Hui-Zhong Zhuang

    IPC分类号： G06F30/30 ,  G06F30/392 ,  H01L21/04 ,  H01L27/02

    CPC分类号： G06F30/392 ,  H01L21/041 ,  H01L27/0207

    摘要： A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

    ELECTRONIC DEVICE SUPPORTING MANUFACTURE OF SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE
    7.
    发明公开
    ELECTRONIC DEVICE SUPPORTING MANUFACTURE OF SEMICONDUCTOR DEVICE AND OPERATING METHOD OF ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240346222A1

    公开(公告)日：2024-10-17

    申请号：US18510969

    申请日：2023-11-16

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jiho Han ,  Jong-Seong Kim ,  Sungju Jang ,  Hyuckjoon Kwon ,  Sunghoon Kim ,  Raehyun Song

    IPC分类号： G06F30/392

    CPC分类号： G06F30/392

    摘要： Disclosed is an operating method of an electronic device that includes a processor and supports manufacture of a semiconductor device. The operating method includes receiving, at the processor, circuit schematics for the manufacture of the semiconductor device, partitioning, at the processor, circuit components of the circuit schematics into at least two mats, calculating, at the processor, availability of placement and routing of the circuit components, based on limited connecting elements electrically connected to the circuit components, for each of the at least two mats, and performing, at the processor, the placement and routing to generate a layout image for the manufacture of the semiconductor device when the availability indicates that the placement and routing is available. The limited connecting elements include vertical lines, which electrically connect an upper portion and a lower portion of the semiconductor device, at limited locations of the semiconductor device.