公开(公告)号：US20240036087A1

公开(公告)日：2024-02-01

申请号：US17815961

申请日：2022-07-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Indranil Som ,  Vaibhav Anantrai Ruparelia ,  Kuppireddy Vasudeva Reddy

IPC: G01R19/04

CPC classification number: G01R19/04

Abstract: Embodiments of the disclosure provide a peak voltage detection circuit with reduced charge loss. A circuit structure of the disclosure includes a peak voltage detector having a first input node coupled to an input line and a second input node coupled to a first electrically actuated switch. The peak voltage detector coupling the first input node and the second input node to an output node, and a second electrically actuated switch coupling the output node of the peak voltage detector to a capacitor. The first electrically actuated switch couples the capacitor to the second input node of the peak voltage detector. The input line is coupled to a control node of the first electrically actuated switch and a control node of the second electrically actuated switch.

公开(公告)号：US11889701B2

公开(公告)日：2024-01-30

申请号：US17237886

申请日：2021-04-22

Applicant: GLOBALFOUNDRIES Dresden Module One Limited Liability Company & Co. KG

Inventor： Tarek Ali ,  Konstantin H. J. Mertens ,  Maximilian W. Lederer ,  David J. Lehninger ,  Konrad Seidel

IPC: H01L21/00 ,  H10B53/30 ,  H01L49/02 ,  H01L29/78 ,  H01L29/51 ,  H10B51/30

CPC classification number: H10B53/30 ,  H01L28/60 ,  H01L29/516 ,  H01L29/78391 ,  H10B51/30

Abstract: Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.

公开(公告)号：US11886021B2

公开(公告)日：2024-01-30

申请号：US17705911

申请日：2022-03-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/02 ,  G02B6/122 ,  G02B6/13 ,  G02B6/30 ,  G02B6/42 ,  G02B6/12

CPC classification number: G02B6/4203 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/13 ,  G02B6/305

Abstract: Photonics structures including a slotted waveguide and methods of fabricating such photonics structures. The photonics structure includes a slotted waveguide having a first waveguide core and a second waveguide core laterally positioned adjacent to the first waveguide core. The first waveguide core is separated from the second waveguide core by a slot. The photonics structure further includes a metamaterial structure having a plurality of elements separated by a plurality of gaps and a dielectric material in the plurality of gaps. The metamaterial structure and the slot of the slotted waveguide are positioned with an overlapping arrangement.

公开(公告)号：US20240028811A1

公开(公告)日：2024-01-25

申请号：US17813344

申请日：2022-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A process design kit (PDK) is supplied to a layout design tool. The PDK includes parameterized cells (Pcells) adapted to cause the layout design tool to automatically add labels to device layouts in the graphic design system (GDS) file that is being created by the layout design tool. Each corresponding label lists parameters used when creating the corresponding device layout. The GDS file is receive back from the layout design tool. The parameters from the labels is applied to corresponding ones of the Pcells within the PDK to create a device verification layout for each of the device layouts in the GDS file. Each of the device layouts in the GDS file is compared to a corresponding device verification layout. The device layouts within the GDS file that fail to match the corresponding device verification layout are thereby identified.

公开(公告)号：US11880065B2

公开(公告)日：2024-01-23

申请号：US17588470

申请日：2022-01-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Steven M. Shank ,  Takako Hirokawa

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/293

CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/29338

Abstract: Structures including an edge coupler and methods of fabricating a structure including an edge coupler. The structure includes an edge coupler having a longitudinal axis, a first ring resonator, and a second ring resonator. The first ring resonator has a first center point that is spaced from the longitudinal axis of the edge coupler by a first perpendicular distance. The second ring resonator has a second center point that is spaced from the longitudinal axis of the edge coupler by a second perpendicular distance.

公开(公告)号：US20240022219A1

公开(公告)日：2024-01-18

申请号：US17864733

申请日：2022-07-14

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Paolo Valerio TESTA ,  Shafiullah SYED

IPC: H03F3/193 ,  H01L29/94

CPC classification number: H03F3/193 ,  H01L29/94 ,  H03F2200/451 ,  H03F2200/72

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a common-gate amplifier circuit and methods of operation. The structure includes at least one well in a substrate, a first metal layer connected to a gate of a transistor circuit, a second metal layer overlapped over the first metal layer to form a capacitor, and a third metal layer connected with vias to the first metal layer and overlapped with the second metal layer to form a second capacitor. At least one capacitance in at least one of a junction between the at least one well and the substrate and between overlapped metal layers of the first metal layer, the second metal layer, and the third metal layer.

公开(公告)号：US11876123B2

公开(公告)日：2024-01-16

申请号：US17214969

申请日：2021-03-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain ,  Renata A. Camillo-Castillo

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L29/737 ,  H01L29/732

CPC classification number: H01L29/66242 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7371 ,  H01L29/732

Abstract: According to a semiconductor device herein, the device includes a substrate. An active device is formed in the substrate. The active device includes a collector region, a base region formed on the collector region, and an emitter region formed on the base region. An isolation structure is formed in the substrate around the active device. A trench filled with a compressive material is formed in the substrate and positioned laterally adjacent to the emitter region and base region. The trench extends at least partially into the collector region.

公开(公告)号：US11869941B2

公开(公告)日：2024-01-09

申请号：US17679166

申请日：2022-02-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Sarah A. McTaggart ,  Rajendran Krishnasamy ,  Qizhi Liu

IPC: H01L21/265 ,  H01L29/732 ,  H01L29/737 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/0817 ,  H01L21/26586 ,  H01L29/66272 ,  H01L29/732 ,  H01L29/7371

Abstract: Disclosed are a structure including a transistor and a method of forming the structure. The transistor includes an emitter region with first and second emitter portions. The first emitter portion extends through a dielectric layer. The second emitter portion is on the first emitter portion and the top of the dielectric layer. An additional dielectric layer covers the top of the second emitter portion. The second emitter portion and the dielectric and additional dielectric layers are wider than the first emitter portion. At least a section of the second emitter portion is narrower than the dielectric and additional dielectric layers, thereby creating cavities positioned vertically between edge portions of the dielectric and additional dielectric layers and positioned laterally adjacent to the second emitter portion. The cavities are filled with dielectric material or dielectric material blocks the side openings to the cavities creating pockets of air, of gas or under vacuum.

公开(公告)号：US20240006491A1

公开(公告)日：2024-01-04

申请号：US17852966

申请日：2022-06-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uppili S. RAGHUNATHAN ,  Vibhor JAIN ,  Qizhi LIU ,  Yves T. NGU ,  Ajay RAMAN ,  Rajendran KRISHNASAMY ,  Alvin J. JOSEPH

IPC: H01L29/10 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with a stepped emitter and methods of manufacture. The structure includes: a collector; a base over the collector; and an emitter over the base, the emitter comprising at least one stepped feature over the base.

公开(公告)号：US20240004140A1

公开(公告)日：2024-01-04

申请号：US17853186

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core. The first waveguide core is positioned in a vertical direction between the second waveguide core and a substrate. The first waveguide core has a first longitudinal axis, the second waveguide core has a second longitudinal axis, and the second longitudinal axis of the second waveguide core is slanted at an angle relative to the first longitudinal axis of the first waveguide core.