Sensor with a membrane electrode, a counterelectrode, and at least one spring

    公开(公告)号:US11505453B2

    公开(公告)日:2022-11-22

    申请号:US16774810

    申请日:2020-01-28

    发明人: Stefan Barzen

    摘要: A sensor includes a membrane electrode, a counter-electrode, and at least one spring. The sensor can include a structure; a membrane electrode, which is deformable as a consequence of pressure and which is in contact with the structure; a counter-electrode mechanically connected to the structure and separated from the membrane electrode by a gap; and at least one spring mechanically connected to the membrane electrode and the counter-electrode, so as to exert an elastic force between the membrane electrode and the counter-electrode.

    Integration of stress decoupling and particle filter on a single wafer or in combination with a waferlevel package

    公开(公告)号:US11505450B2

    公开(公告)日:2022-11-22

    申请号:US17076250

    申请日:2020-10-21

    摘要: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate having a first surface and a second surface arranged opposite to the first surface; a stress-sensitive sensor disposed at the first surface of the substrate, where the stress-sensitive sensor is sensitive to mechanical stress; a stress-decoupling trench that has a vertical extension that extends from the first surface into the substrate, where the stress-decoupling trench vertically extends partially into the substrate towards the second surface although not completely to the second surface; and a plurality of particle filter trenches that vertically extend from the second surface into the substrate, wherein each of the plurality of particle filter trenches have a longitudinal extension that extends orthogonal to the vertical extension of the stress-decoupling trench.

    SEMICONDUCTOR DEVICE WITH TERMINATION STRUCTURE AND FIELD-FREE REGION

    公开(公告)号:US20220359314A1

    公开(公告)日:2022-11-10

    申请号:US17737492

    申请日:2022-05-05

    IPC分类号: H01L21/66 G01K7/01 G01K7/16

    摘要: A semiconductor device includes a semiconductor portion with a first surface at a front side, wherein the semiconductor portion includes an active area, a termination structure laterally surrounding the active area, and a field-free region between the termination structure and a lateral outer surface of the semiconductor portion. The field-free region includes a probe contact region and a main portion. The probe contact region and the main portion form a semiconductor junction. A probe pad on the first surface and the probe contact region form an ohmic contact. A protection passivation layer on the first surface is formed on at least the termination structure and exposes the probe pad.

    SERIAL PERIPHERAL INTERFACE (SPI) AUTOMATIC REGISTER ADDRESS INCREMENTATION ACROSS DATA FRAMES

    公开(公告)号:US20220358077A1

    公开(公告)日:2022-11-10

    申请号:US17314203

    申请日:2021-05-07

    摘要: A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.

    Semiconductor device
    98.
    发明授权

    公开(公告)号:US11495593B2

    公开(公告)日:2022-11-08

    申请号:US17085661

    申请日:2020-10-30

    摘要: A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m1, with m1≥0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m12. The first partial junction grading coefficient m11 is different to the second partial junction grading coefficient m12, with m11≠m12. At least one of the first and second partial junction grading coefficients m11, m12 is greater than 0.50, with m11 and/or m12>0.50. The first junction grading coefficient m1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m11, m12.

    Microcontroller and power management integrated circuit application clustering for safe state management

    公开(公告)号:US11493982B2

    公开(公告)日:2022-11-08

    申请号:US17152862

    申请日:2021-01-20

    IPC分类号: G06F1/3234 G06F1/3206

    摘要: Systems, methods, and circuitries are provided for controlling a microcontroller (MCU) on a per-application basis. A control system includes a microcontroller unit (MCU) including a first application group and a second application group. The first application group includes at least one hardware component not associated with the second application group. The control system includes a power management integrated circuit (PMIC). The PMIC includes monitoring circuitry configured to monitor the first application group to detect a first application group fault condition and monitor the second application group to detect a second application group fault condition. Based on the monitoring, the PMIC provides a first reset signal to the first application group that does not reset the second application group or provides a second reset signal to the second application group that does not reset the first application group.

    FAST SECURE BOOTING METHOD AND SYSTEM

    公开(公告)号:US20220350891A1

    公开(公告)日:2022-11-03

    申请号:US17243834

    申请日:2021-04-29

    IPC分类号: G06F21/57 H04L9/32

    摘要: A method to secure boot an electronic device is disclosed according to some embodiments. The method includes receiving a request to initiate a boot sequence using memory content stored in a non-volatile memory circuit. A secure boot circuit receives verification data from the non-volatile memory circuit indicating the memory content. The verification data includes an error correction code for the memory content without including all of the memory content. A cryptographic hashing operation is performed to the error correction code in the secure boot circuit to obtain a digest of the error correction code. The digest is compared with a pre-stored reference digest to generate a verification signal. The verification signal is provided to the electronic device indicating whether the boot sequence passes the verification.