公开(公告)号：US20060017482A1

公开(公告)日：2006-01-26

申请号：US11148947

申请日：2005-06-09

Applicant: Virender Chauhan ,  Paras Garg

Inventor： Virender Chauhan ,  Paras Garg

IPC: H03K3/037

CPC classification number: H03K3/3565

Abstract: A compensated Schmitt Trigger circuit for providing a monotonic hysterisis response, the circuit including a plurality of transistors connected in series and coupled to a common input signal at their control inputs, a feedback circuit connected to the output of the plurality of transistors, an inverter coupled to the output of the plurality of transistors and to the feedback circuit for providing a hysterisis response at higher supply voltage, wherein the feedback circuit includes at least one feedback element coupled between the output of said plurality of transistors and input of the inverter for providing a monotonic hysterisis response at the output node of the Schmitt Trigger circuit. The feedback elements are connected/disconnected by control signals that reflect the variations in PVT conditions, and the control signals are derived from the standard Input/Output circuits library for compensation.

Abstract translation: 一种用于提供单调滞后响应的补偿施密特触发电路，该电路包括串联连接并耦合到其控制输入处的公共输入信号的多个晶体管，连接到多个晶体管的输出端的反馈电路， 耦合到多个晶体管的输出端和反馈电路，用于在较高的电源电压下提供滞后响应，其中反馈电路包括耦合在所述多个晶体管的输出和反相器的输入端之间的至少一个反馈元件， 施密特触发电路输出节点的单调滞后响应。 反馈元件通过反映PVT条件变化的控制信号连接/断开，控制信号从标准输入/输出电路库导出，用于补偿。

公开(公告)号：US20050235236A1

公开(公告)日：2005-10-20

申请号：US10928627

申请日：2004-08-27

Applicant: Sunil Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

Inventor： Sunil Sharma ,  Ajay Tomar ,  Dhabalendu Samanta

IPC: G06F9/45 ,  G06F17/50

CPC classification number: G06F17/5054

Abstract: A method for finding a maximum volume and minimum cutset in a network of interconnected nodes is provided. The method is applicable to systems that can be reduced to such a network, including telecommunication networks, traffic networks, computer networks, layouts, hydraulic networks, etc. An equivalent network is derived by replacing all nodes other then the source and sink by two interconnected nodes. A conventional method applies an augmenting path algorithm that identifies a cutset. If the feasible cutset is not achieved then a reduced network is constructed by directly connecting the member nodes of identified cutsets to the source node and repeating the above process for the reduced network until a feasible cutset is achieved.

Abstract translation: 提供了一种用于在互连节点的网络中找到最大容量和最小剪切的方法。 该方法适用于可以减少到这样的网络的系统，包括电信网络，业务网络，计算机网络，布局，液压网络等。通过将所有节点替换为源和汇两个互连的所有节点而导出等效网络 节点。 常规方法应用识别切片的增强路径算法。 如果没有实现可行的切割，则通过将识别的切割器的成员节点直接连接到源节点并且对于减少的网络重复上述过程，直到实现可行的切片来构造缩小的网络。

公开(公告)号：US20050179469A1

公开(公告)日：2005-08-18

申请号：US10985661

申请日：2004-11-10

Applicant: Sunil Kasanyal ,  Hari Dubey

Inventor： Sunil Kasanyal ,  Hari Dubey

IPC: H03K5/13 ,  H03K5/22 ,  H04L25/02

CPC classification number: H04L25/0286 ,  H03K5/133 ,  H04L25/0272

Abstract: The present invention provides a Differential Signaling line driver including a pre-emphasis circuit, which boosts the output drive current without any delay whenever there is a transition in the input signal to the driver, using the input signal itself to provide the pre-emphasis through a current steering circuit that switches the direction of drive currents to provide a differential output signal. A delayed signal is then used to disable the pre-emphasis after a short period.

Abstract translation: 本发明提供了一种差分信号线路驱动器，其包括预加重电路，每当输入信号转换到驱动器时​​，无需任何延迟即可提升输出驱动电流，使用输入信号本身提供预加重 电流转向电路，其切换驱动电流的方向以提供差分输出信号。 然后使用延迟信号在短时间之后禁用预加重。

公开(公告)号：US20050174102A1

公开(公告)日：2005-08-11

申请号：US11025854

申请日：2004-12-29

Applicant: Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

Inventor： Ruchir Saraswat ,  Balwant Singh ,  Prashant Dubey

IPC: G01R19/00 ,  G01R31/28 ,  G01R31/30

CPC classification number: G01R31/2884 ,  G01R31/3004

Abstract: An apparatus for enabling the on-chip analysis of the voltage and/or current transition behaviour of one or more embedded nets of an integrated circuit independently of the fabrication process. The said apparatus comprises a Reference Step Generator (RSG) for providing programmable reference voltages or currents, a Step Delay Generator (SDG) for providing programmable delays, a Comparator (C) that receives the output of the reference step generator on one input, the output from the node under test at the second input, and a latch enable signal from the step delay generator, and provides a latched digital output in response to the comparison, and a controller that co-ordinates the operation of the reference step generator, Step Delay Generator and Latching Comparator to provide a transient response measurement.

Abstract translation: 一种用于独立于制造过程实现片上分析集成电路的一个或多个嵌入网络的电压和/或电流转换特性的装置。 所述装置包括用于提供可编程参考电压或电流的参考步长发生器（RSG），用于提供可编程延迟的步进延迟发生器（SDG）;在一个输入端接收参考步进发生器的输出的比较器（C） 在来自第二输入的被测节点的输出以及来自阶梯延迟发生器的锁存使能信号，并且响应于该比较而提供锁存的数字输出;以及控制器，其对参考步长发生器的操作进行调节，步骤 延迟发生器和锁存比较器提供瞬态响应测量。

公开(公告)号：US06894541B2

公开(公告)日：2005-05-17

申请号：US10684076

申请日：2003-10-10

Applicant: Vivek Nautiyal ,  Ashish Kumar

Inventor： Vivek Nautiyal ,  Ashish Kumar

IPC: G01R15/00 ,  G11C7/02 ,  G11C7/06 ,  H03F3/45

CPC classification number: G11C7/065 ,  G11C7/02

Abstract: A sense amplifier includes a feedback controlled bit line access scheme that feeds a sense amplifier output signal back to control operation of its associated bit line access transistor. This feedback may be implemented using a pair of inverter circuits each coupling a respective output signal to the control gate of the associated access transistor. Alternatively, the feedback may be implement using a logic gate which logically combines the sense amplifier output signals together to generate an output signal for controlling operation of both access transistors. The logic gate is preferably a NAND gate. The sense amplifier further includes a cross-connected feedback inversion circuit which inverts a sense amplifier output signal from a first latch inverter for application to a conducting line of a second latch inverter.

Abstract translation: 读出放大器包括反馈控制的位线访问方案，其将读出放大器输出信号反馈到其相关联的位线存取晶体管的操作。 该反馈可以使用一对逆变器电路来实现，每个逆变器电路将相应的输出信号耦合到相关联的存取晶体管的控制栅极。 或者，可以使用将读出放大器输出信号逻辑地组合在一起以产生用于控制两个存取晶体管的操作的输出信号的逻辑门来实现反馈。 逻辑门优选地是NAND门。 读出放大器还包括一个交叉连接的反馈反相电路，它将来自第一锁存逆变器的读出放大器输出信号反相，以应用于第二锁存逆变器的导线。

公开(公告)号：US20040153923A1

公开(公告)日：2004-08-05

申请号：US10667199

申请日：2003-09-18

Applicant: STMicroelectronics Pvt, Ltd.

Inventor： Ashish Kumar Goel ,  Namerita Khanna ,  Davinder Aggarwal

IPC: G01R031/28

CPC classification number: G06F11/1402 ,  G01R31/318519 ,  G06F11/1008

Abstract: An improved method and apparatus for reloading frames in which errors are detected during the Programmable Logic Device configuration. A configuration data frame for a FPGA is loaded to the Frame register of the FPGA and also to an error detection circuit which detects errors with the loaded frame. An error counter value is maintained by the apparatus and is incremented each time an error with a frame is detected. The incremented value is compared by a Comparator circuit with a pre-determined threshold value nullnnull. If a match is found then the configuration process is aborted, else the data frame is reloaded in the configuration memory, transferred again to the frame register and rechecked for errors. If no error is detected with the reloaded frame, the error counter value is reset and the next frame is loaded until the FPGA configuration process is over.

Abstract translation: 一种用于重新加载在可编程逻辑器件配置期间检测到错误的帧的改进的方法和装置。 FPGA的配置数据帧被加载到FPGA的帧寄存器，并且还加载到检测错误的错误检测电路。 错误计数器值由设备维护，并且每当检测到帧的错误时递增。 递增值由具有预定阈值“n”的比较器电路进行比较。 如果发现匹配，则配置过程将中止，否则数据帧将重新加载到配置存储器中，再次传输到帧寄存器并重新检查错误。 如果在重新加载的帧中没有检测到错误，错误计数器值将被复位，下一个帧被加载，直到FPGA配置过程结束。

公开(公告)号：US20040136253A1

公开(公告)日：2004-07-15

申请号：US10679941

申请日：2003-10-06

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Anuj Gupta ,  Sanjeev Chopra

IPC: G11C007/00

CPC classification number: G11C7/065

Abstract: An improved latch-type sense amplifier circuit having two cross-coupled inverters forming a latch, a supply coupling device for selectively connecting the latch to a supply source, and a bit line coupling circuits for selectively connecting the inputs of each inverter to the complimentary bit line from the memory array. The circuit is configured to sense a voltage difference between the bit lines with improved reliability by providing a delayed sense amplifier enable signal to pass transistors for delaying disconnection of the bit lines from the sense amplifier until the latching action is completed, and adding two transistors in series with the existing transistors of the conventional latch for correcting the offset between the threshold voltages of the inverters of the latch.

Abstract translation: 具有形成锁存器的两个交叉耦合的反相器的改进的锁存型读出放大器电路，用于选择性地将锁存器连接到电源的电源耦合装置和用于选择性地将每个反相器的输入连接到补充位的位线耦合电路 线从内存阵列。 该电路被配置为通过提供延迟读出放大器使能信号来传递晶体管来延迟位线从读出放大器的断开直到闭锁动作完成，并且将两个晶体管加到 与常规锁存器的现有晶体管串联，用于校正锁存器的反相器的阈值电压之间的偏移。

公开(公告)号：US20040108875A1

公开(公告)日：2004-06-10

申请号：US10662952

申请日：2003-09-12

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajesh Kaushik ,  Rajesh Narwal

IPC: H03B001/00

CPC classification number: H03K17/166

Abstract: A CMOS output buffer uses feedback from a ground node to reduce ground bounce by utilizing a tolerable ground bounce limit, making it less sensitive to operating conditions and processing parameters. An input to the NMOS device of the output buffer is provided by the output of a control element which receives a first input from a pre-driver and a second input (i.e., the feedback) from the ground node.

Abstract translation: CMOS输出缓冲器使用来自接地节点的反馈，通过利用可容忍的接地反弹限制来减少接地反弹，使其对工作条件和处理参数的敏感性降低。 输出缓冲器的NMOS器件的输入由从接地节点接收来自预驱动器的第一输入和第二输入（即，反馈）的控制元件的输出提供。

公开(公告)号：US20040061524A1

公开(公告)日：2004-04-01

申请号：US10611322

申请日：2003-07-01

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Sunil Chandra Kasanyal

IPC: H03K019/0175

CPC classification number: H03K19/018521

Abstract: A voltage level translator for digital logic circuits provides high level to low level voltage translation with equal rise and fall delays. The voltage level translator may include an input high voltage logic inverter (operating at the high voltage level) and connected to an output low voltage logic inverter operating at the low voltage level via a voltage reduction circuit. A related method for providing high level to low voltage translation may include providing an input inverter operating at the high voltage level and an output inverter operating at the low voltage level. Furthermore, the output of the high voltage inverter may be coupled to the input of the low voltage inverter after reducing the output voltage of the high voltage inverter to the required level.

Abstract translation: 用于数字逻辑电路的电压电平转换器具有相同的上升和下降延迟的高电平到低电平电压转换。 电压电平转换器可以包括输入高压逻辑逆变器（以高电压电平工作），并通过电压降低电路连接到在低电压电平下工作的输出低压逻辑逆变器。 用于提供高电平到低电压平移的相关方法可以包括提供在高电压电平下工作的输入逆变器和在低电压电平下工作的输出逆变器。 此外，在将高压逆变器的输出电压降低到所需水平之后，高压逆变器的输出可以耦合到低压逆变器的输入。

公开(公告)号：US20030172363A1

公开(公告)日：2003-09-11

申请号：US10347139

申请日：2003-01-17

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Rajat Chauhan ,  Rajesh Kaushik

IPC: G06F017/50

CPC classification number: H03K19/17748 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744

Abstract: A method and an improved FPGA apparatus for enabling the selective deployment of unused flip-flops or other circuit elements in IO cells and unused decoders or other circuit elements in Look Up Tables (LUT), for core logic functions is provided, comprising disconnecting means for selectively disconnecting unused circuit elements from the IO pad circuitry or from said LUT circuitry, and connecting means for selectively connecting said disconnected circuit elements either to the connection matrix of the core logic or between themselves to provide independently configured functions.

Abstract translation: 提供了一种方法和改进的FPGA装置，用于在核心逻辑功能中使得能够选择性地部署IO单元中的未使用的触发器或其他电路元件以及查找表（LUT）中的未使用的解码器或其他电路元件，包括用于 有选择地从IO垫电路或所述LUT电路断开未使用的电路元件，以及连接装置，用于选择性地将所述断开的电路元件连接到核心逻辑的连接矩阵或它们之间，以提供独立配置的功能。