公开(公告)号：US11532987B2

公开(公告)日：2022-12-20

申请号：US17226941

申请日：2021-04-09

申请人： Halo Microelectronics Co., Ltd.

发明人： Shuang Han ,  Hai Tao ,  Rui Liu ,  Jun Fan ,  Liang Zhao

IPC分类号： H02M3/07 ,  H02M1/00 ,  H02M3/158 ,  H02M3/157 ,  H02J7/00

摘要： An apparatus includes a first group of switches connected in series, a second group of switches connected in series, a first flying capacitor between a first common node and a third common node of the first group of switches, a second flying capacitor between a first common node and a third common node of the second group of switches, wherein the first group of switches and the second group of switches are configured such that the apparatus operates in one of three operating modes including a bypass operating mode, a hybrid operating mode and a boost/buck operating mode.

公开(公告)号：US11532748B2

公开(公告)日：2022-12-20

申请号：US17034176

申请日：2020-09-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Po-Chi Wu ,  Chai-Wei Chang ,  Jung-Jui Li ,  Ya-Lan Chang ,  Yi-Cheng Chao

IPC分类号： H01L21/8238 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

摘要： A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a substrate. The dielectric layer has a trench passing through the dielectric layer. The method includes forming a gate stack in the trench. The method includes performing a hydrogen-containing plasma process over the gate stack. The method includes removing a top portion of the gate stack to form a first recess surrounded by the gate stack and the dielectric layer. The method includes forming a cap layer in the first recess to fill the first recess.

公开(公告)号：US11532723B2

公开(公告)日：2022-12-20

申请号：US16870429

申请日：2020-05-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC分类号： H01L29/165 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/311 ,  H01L29/06 ,  H01L21/027 ,  H01L29/423 ,  H01L29/51 ,  H01L29/10 ,  H01L27/088 ,  H01L21/762

摘要： A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

公开(公告)号：US11532714B2

公开(公告)日：2022-12-20

申请号：US17093345

申请日：2020-11-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L21/8234 ,  H01L23/528

摘要： A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

公开(公告)号：US11532713B2

公开(公告)日：2022-12-20

申请号：US17091159

申请日：2020-11-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC分类号： H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

摘要： A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US11532567B2

公开(公告)日：2022-12-20

申请号：US16568983

申请日：2019-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Hua Yu ,  Shin-Puu Jeng ,  Der-Chyang Yeh ,  Hsien-Wei Chen ,  Jie Chen

IPC分类号： H01L23/552 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/10 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/58 ,  H01L23/498

摘要： A package includes a device die, a molding material molding the device die therein, and a through-via penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via. A metal ring is close to edges of the package, wherein the metal ring is coplanar with the redistribution line.

公开(公告)号：US11532519B2

公开(公告)日：2022-12-20

申请号：US17340660

申请日：2021-06-07

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yi-Bo Liao ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC分类号： H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/092

摘要： In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

公开(公告)号：US11532512B2

公开(公告)日：2022-12-20

申请号：US17062822

申请日：2020-10-05

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Che-Cheng Chang ,  Chih-Han Lin

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L23/532

摘要： A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

公开(公告)号：US11532509B2

公开(公告)日：2022-12-20

申请号：US16884837

申请日：2020-05-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chung-Chiang Wu ,  Po-Cheng Chen ,  Kuo-Chan Huang ,  Pin-Hsuan Yeh ,  Wei-Chin Lee ,  Hsien-Ming Lee ,  Chien-Hao Chen ,  Chi On Chui

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L29/423

摘要： A method includes forming a gate electrode on a semiconductor region, recessing the gate electrode to generate a recess, performing a first deposition process to form a first metallic layer on the gate electrode and in the recess, wherein the first deposition process is performed using a first precursor, and performing a second deposition process to form a second metallic layer on the first metallic layer using a second precursor different from the first precursor. The first metallic layer and the second metallic layer comprise a same metal. The method further incudes forming a dielectric hard mask over the second metallic layer, and forming a gate contact plug penetrating through the dielectric hard mask. The gate contact plug contacts a top surface of the second metallic layer.

公开(公告)号：US11532437B2

公开(公告)日：2022-12-20

申请号：US16605693

申请日：2018-04-17

申请人： TDK Electronics AG

发明人： Thomas Puerstinger

IPC分类号： H01G4/30 ,  H01G4/012 ,  H01G4/12 ,  H01G4/236

摘要： A multilayer device and a method for producing a multilayer device are disclosed. In an embodiment a multilayer device includes a main body having at least two external electrodes, at least one first internal electrode; at least one second internal electrode, wherein each internal electrode is electrically conductively connected to an external electrode, a plurality of ceramic layers, wherein the ceramic layers comprise the internal electrodes and at least one dielectric layer, wherein, viewed along a stack direction of the ceramic layers, the dielectric layer being arranged between the internal electrodes, and wherein the dielectric layer is printed onto at least one sub-region of one of the ceramic layers.