公开(公告)号：US20080153224A1

公开(公告)日：2008-06-26

申请号：US11735229

申请日：2007-04-13

申请人： Connie Pin Chin Wang ,  Simon Siu-Sing Chan ,  Angela T. Hui ,  Paul R. Besser ,  Shenqing Fang

发明人： Connie Pin Chin Wang ,  Simon Siu-Sing Chan ,  Angela T. Hui ,  Paul R. Besser ,  Shenqing Fang

IPC分类号： H01L21/336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.

摘要翻译： 提供了一种集成电路系统，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在外部掺杂区域上形成接触，减少接触以形成变薄的接触，以及 在变薄的触点上形成金属插头。

公开(公告)号：US07361587B1

公开(公告)日：2008-04-22

申请号：US10934923

申请日：2004-09-02

申请人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

发明人： Wenmei Li ,  Angela T. Hui ,  Dawn Hopper ,  Kouros Ghandehari

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76831 ,  Y10S438/97

摘要： The present invention is a semiconductor contact formation system and methods that form contact insulation regions comprising multiple etch stop sublayers that facilitate formation of contacts. This contract formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop contact formation process in which a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region width are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.

摘要翻译： 本发明是形成接触绝缘区域的半导体接触形成系统和方法，该接触绝缘区域包括有助于形成接触的多个蚀刻停止子层。 该契约形成过程提供相对较小的衬底连接，同时解决了形成具有小尺寸的接触孔的关键平版印刷限制问题。 在一个实施例中，多次蚀刻停止触点形成工艺，其中沉积包括多个蚀刻停止层的多重蚀刻停止绝缘层。 通过选择性地去除（例如，蚀刻）多个蚀刻停止绝缘层中的一些，在多个蚀刻停止绝缘层中形成接触区域。 在一个实施例中，多个蚀刻停止绝缘层的较大部分被去除靠近金属层，并且较小的部分被移除到靠近基板的位置。 不同的接触区域宽度通过执行由多个蚀刻停止绝缘层中的多个蚀刻停止层控制的多个蚀刻工艺和间隔物形成以在底部收缩接触尺寸来实现。 导电材料（例如，钨）沉积在接触区域中。

公开(公告)号：US07323418B1

公开(公告)日：2008-01-29

申请号：US11102004

申请日：2005-04-08

申请人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

发明人： Minh Van Ngo ,  Angela T. Hui ,  Sergey D. Lopatin

IPC分类号： H01L21/302

CPC分类号： G11C13/0016 ,  G11C13/0014 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/14 ,  H01L45/1608 ,  H01L45/1683 ,  H01L51/0591

摘要： The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

摘要翻译： 本发明利用回蚀工艺来提供用于聚合物存储元件的电极帽。 这允许聚合物存储元件形成在嵌入在衬底上形成的层中的通孔内。 通过利用回蚀工艺，本发明提供了利用通孔的聚合物存储器件的适当功能所需的微小电触点。 在本发明的一个实例中，在电介质层中形成一个或多个通孔以露出下层。 然后在下层上的通孔内形成聚合物层，其中沉积在聚合物层上的顶部电极材料层填充通孔的剩余部分。 然后通过蚀刻工艺去除顶部电极材料的多余部分以形成提供聚合物存储元件的电接触点的电极帽。

公开(公告)号：US07301193B2

公开(公告)日：2007-11-27

申请号：US10762445

申请日：2004-01-22

申请人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Shenqing Fang ,  Timothy Thurgate ,  Kuo-Tung Chang ,  Richard Fastow ,  Angela T. Hui ,  Kazuhiro Mizutani ,  Kelwin Ko ,  Hiroyuki Kinoshita ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L29/788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/743 ,  H01L29/41766 ,  H01L29/66636

摘要： According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

摘要翻译： 根据一个示例性实施例，浮动栅极存储器单元包括位于衬底上并位于衬底中的沟道区域上方的堆叠栅极结构。 浮动栅极存储单元还包括形成在衬底中的与堆叠的栅极结构相邻的凹部，其中凹部具有侧壁，底部和深度。 根据该示例性实施例，浮动栅极存储单元还包括位于与凹部的侧壁相邻并位于堆叠栅极结构下方的源极。 浮动栅极存储单元还包括位于凹部底部下方和源极之下的Vss连接区域，其中Vss连接区域连接到源极。 位于凹部底部下方的Vss连接区使得源在通道区域中具有减小的横向扩散。

公开(公告)号：US07300886B1

公开(公告)日：2007-11-27

申请号：US11147208

申请日：2005-06-08

申请人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

发明人： Minh Van Ngo ,  Ning Cheng ,  Wenmei Li ,  Angela T. Hui ,  Pei-Yuan Gao ,  Robert A. Huertas

IPC分类号： H01L21/31

CPC分类号： H01L21/31625 ,  H01L21/02129 ,  H01L21/02271 ,  H01L27/115 ,  H01L27/11568

摘要： A method of manufacturing a memory device includes forming a first dielectric layer over a substrate and forming a charge storage element over the first dielectric layer. The method also includes forming a second dielectric layer over the charge storage element and forming a control gate over the second dielectric layer. The method further includes depositing an interlayer dielectric over the control gate at a high temperature.

摘要翻译： 一种制造存储器件的方法包括在衬底上形成第一介电层，并在第一介电层上形成电荷存储元件。 该方法还包括在电荷存储元件上形成第二电介质层，并在第二电介质层上形成控制栅极。 该方法还包括在高温下在控制栅极上沉积层间电介质。

公开(公告)号：US07285499B1

公开(公告)日：2007-10-23

申请号：US11127175

申请日：2005-05-12

申请人： Scott A. Bell ,  Phillip Lawrence Jones ,  Angela T. Hui

发明人： Scott A. Bell ,  Phillip Lawrence Jones ,  Angela T. Hui

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/76802

摘要： A method includes forming a group of first structures on a semiconductor device and forming spacers adjacent side surfaces of each of the first structures to form a group of second structures. The method further includes using the group of second structures to form at least one sub-lithographic opening in a material layer located below the group of second structures.

摘要翻译： 一种方法包括在半导体器件上形成一组第一结构，并且在每个第一结构的邻近侧面上形成间隔物以形成一组第二结构。 该方法还包括使用该组第二结构在位于第二结构组下面的材料层中形成至少一个亚光刻开口。

公开(公告)号：US07015135B2

公开(公告)日：2006-03-21

申请号：US10316569

申请日：2002-12-10

申请人： Angela T. Hui ,  Wenmei Li ,  Amy C. Tu

发明人： Angela T. Hui ,  Wenmei Li ,  Amy C. Tu

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802

摘要： A method and system for providing at least one contact in a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating layer on the interlayer dielectric, and at least one feature below the etch stop layer. A resist mask having an aperture and residing on the anti-reflective coating layer is provided. The aperture is above an exposed portion of the anti-reflective coating layer. The method and system include etching the exposed anti-reflective coating layer and the underlying interlayer dielectric without etching through the etch stop layer, thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

摘要翻译： 一种用于在半导体器件中提供至少一个触点的方法和系统。 半导体器件包括衬底，蚀刻停止层，蚀刻停止层上的层间电介质，层间电介质上的抗反射涂层，以及蚀刻停止层下方的至少一个特征。 提供具有孔径并且位于抗反射涂层上的抗蚀剂掩模。 孔径在抗反射涂层的暴露部分之上。 该方法和系统包括蚀刻暴露的抗反射涂层和下层层间电介质，而不通过蚀刻停止层进行蚀刻，由此提供至少一个接触孔的一部分。 该方法和系统还包括在原位去除抗蚀剂掩模，去除暴露在接触孔部分中的一部分蚀刻停止层，并用导电材料填充该接触孔。

公开(公告)号：US06867097B1

公开(公告)日：2005-03-15

申请号：US09430366

申请日：1999-10-28

申请人： Mark T. Ramsbey ,  Robert B. Ogle ,  Tommy C. Hsiao ,  Angela T. Hui ,  Tuan Duc Pham ,  Marina V. Plat ,  Lewis Shen

发明人： Mark T. Ramsbey ,  Robert B. Ogle ,  Tommy C. Hsiao ,  Angela T. Hui ,  Tuan Duc Pham ,  Marina V. Plat ,  Lewis Shen

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/31053 ,  H01L21/3144 ,  H01L21/31612

摘要： An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

摘要翻译： 制造包括具有第一厚度的浮动栅极的衬底的闪存单元的改进方法包括在衬底上并在浮动栅极上沉积绝缘体。 绝缘体优选是高质量的氧化物。 不覆盖浮动栅极的绝缘体的一部分具有大于浮栅的第一厚度的第二厚度。 该方法还包括抛光绝缘体，直到第二厚度基本上等于第一厚度。 抛光导致平面浮栅和绝缘体层。 该方法还包括在平面浮置栅极和绝缘体层上依次沉积介电层和控制栅极层，然后蚀刻这些层以完成存储单元的堆叠栅极结构。

公开(公告)号：US06867063B1

公开(公告)日：2005-03-15

申请号：US10262221

申请日：2002-09-30

申请人： Kouros Ghandehari ,  Dawn Hopper ,  Wenmei Li ,  Angela T. Hui

发明人： Kouros Ghandehari ,  Dawn Hopper ,  Wenmei Li ,  Angela T. Hui

IPC分类号： G03F7/09 ,  H01L21/027 ,  H01L21/02

CPC分类号： G03F7/091 ,  H01L21/0276

摘要： A method of manufacturing a semiconductor. A conventional bottom anti-reflective coating is applied over a reflective surface, for example an inter-layer dielectric. A second anti-reflective coating is deposited over the first anti-reflective coating. The second anti-reflective coating is organic and may be deposited through a spin-on process. The organic anti-reflective coating may be deposited with more exacting optical properties and better control of the layer thickness than conventional bottom anti-reflective coatings applied via chemical vapor deposition processes. The combination of the two layers of anti-reflective materials, the materials having differing optical properties, demonstrates superior control of reflections from underlying materials compared with conventional art methods. More particularly, an organic anti-reflective coating in conjunction with an inorganic anti-reflective coating may cancel reflections across a wide range of thicknesses in an underlying dielectric layer. The superior anti-reflective structure of embodiments of the present invention allow patterning of semiconductor structures at smaller critical dimensions with greater accuracy, rendering competitive advantages in device speed, density and cost.

摘要翻译： 一种制造半导体的方法。 常规的底部抗反射涂层施加在反射表面上，例如层间电介质。 在第一抗反射涂层上沉积第二抗反射涂层。 第二种抗反射涂层是有机的，可通过旋涂工艺沉积。 与通过化学气相沉积工艺施加的常规底部抗反射涂层相比，有机抗反射涂层可以沉积更加严格的光学性能和更好的层厚度控制。 与传统技术方法相比，两层抗反射材料（具有不同光学性质的材料）的组合表现出对来自下层材料的反射的优异控制。 更具体地，结合无机抗反射涂层的有机抗反射涂层可以消除底层电介质层中宽范围的厚度的反射。 本发明的实施例的优异的抗反射结构允许以较小的临界尺寸更精确地图案化半导体结构，从而在装置速度，密度和成本方面具有竞争优势。

公开(公告)号：US06808992B1

公开(公告)日：2004-10-26

申请号：US10150240

申请日：2002-05-15

申请人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

发明人： Kelwin Ko ,  Shenqing Fang ,  Angela T. Hui ,  Hiroyuki Kinoshita ,  Wenmei Li ,  Yu Sun ,  Hiroyuki Ogawa

IPC分类号： H01L21336

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L29/6656

摘要： A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

摘要翻译： 描述了一种用于提供半导体器件的方法和系统。 半导体器件包括衬底，芯和周边。 芯包括具有第一多个边缘的多个核心栅极叠层，而周边具有多个具有第二多个边缘的外围栅极堆叠。 该方法和系统包括提供多个芯间隔件，多个外围间隔件，多个芯源和多个导电区域。 芯间隔件位于第一多个边缘处并且具有厚度。 外围间隔件位于第二多个边缘处并且具有大于第一厚度的第二厚度。 核心源位于多个核心门堆栈之间。 导电区域在多个核心源上。 该方法允许不同厚度的间隔件形成在芯部和周边中，使得间隔件可以根据芯部和周边的不同要求进行调整。