公开(公告)号：US06867097B1

公开(公告)日：2005-03-15

申请号：US09430366

申请日：1999-10-28

申请人： Mark T. Ramsbey ,  Robert B. Ogle ,  Tommy C. Hsiao ,  Angela T. Hui ,  Tuan Duc Pham ,  Marina V. Plat ,  Lewis Shen

发明人： Mark T. Ramsbey ,  Robert B. Ogle ,  Tommy C. Hsiao ,  Angela T. Hui ,  Tuan Duc Pham ,  Marina V. Plat ,  Lewis Shen

IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L21/31053 ,  H01L21/3144 ,  H01L21/31612

摘要： An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

摘要翻译： 制造包括具有第一厚度的浮动栅极的衬底的闪存单元的改进方法包括在衬底上并在浮动栅极上沉积绝缘体。 绝缘体优选是高质量的氧化物。 不覆盖浮动栅极的绝缘体的一部分具有大于浮栅的第一厚度的第二厚度。 该方法还包括抛光绝缘体，直到第二厚度基本上等于第一厚度。 抛光导致平面浮栅和绝缘体层。 该方法还包括在平面浮置栅极和绝缘体层上依次沉积介电层和控制栅极层，然后蚀刻这些层以完成存储单元的堆叠栅极结构。

公开(公告)号：US06365509B1

公开(公告)日：2002-04-02

申请号：US09586556

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Wenge Yang ,  Marina V. Plat ,  Lewis Shen

发明人： Ramkumar Subramanian ,  Wenge Yang ,  Marina V. Plat ,  Lewis Shen

IPC分类号： H01L214763

CPC分类号： H01L21/76802 ,  H01L21/76895 ,  H01L27/115

摘要： A method is provided for manufacturing a semiconductor with fewer steps and minimized variation in the etching process by using SiON as a bottom antireflective (BARC) layer and hard mask in conjunction with a thin photoresist layer. In one embodiment, an etch-stop layer is deposited on a semiconductor substrate, a dielectric layer is deposited on top of the etch-stop layer, a BARC is deposited on top of the dielectric layer, and a photoresist layer with a thickness less than the thickness of the BARC is then deposited on top of the BARC. The photoresist is then patterned, photolithographically processed, and developed. The BARC is then etched away in the pattern developed on the photoresist and to photoresist is then removed. The BARC is then used as a mask for the etching of the dielectric layer and is subsequently removed in the process of etchings the dielectric and etch-stop layers without the benefit of a separate BARC-removal step.

摘要翻译： 提供了一种通过使用SiON作为底部抗反射（BARC）层和与薄的光致抗蚀剂层结合的硬掩模来制造具有较少步骤和最小化蚀刻工艺的半导体的方法。 在一个实施例中，蚀刻停止层沉积在半导体衬底上，电介质层沉积在蚀刻停止层的顶部，BARC沉积在电介质层的顶部，并且光致抗蚀剂层的厚度小于 然后将BARC的厚度沉积在BARC的顶部。 然后将光致抗蚀剂图案化，光刻加工和显影。 然后将BARC以在光致抗蚀剂上显影的图案蚀刻掉，然后除去光致抗蚀剂。 然后将BARC用作蚀刻电介质层的掩模，随后在蚀刻电介质层和蚀刻停止层的过程中除去，而不需要单独的BARC去除步骤。

公开(公告)号：US06586339B1

公开(公告)日：2003-07-01

申请号：US09428918

申请日：1999-10-28

申请人： Marina V. Plat ,  Robert Ogle ,  Lewis Shen

发明人： Marina V. Plat ,  Robert Ogle ,  Lewis Shen

IPC分类号： H01L21302

CPC分类号： G03F7/091 ,  H01L21/0276 ,  H01L21/32139

摘要： A thin barrier layer of undoped silicon is formed on an ARC to prevent resist poisoning and footing. The silicon layer can be removed with improved yield and high selectivity with respect to the underlying gate dielectric layer, thereby avoiding degradation of the gate dielectric layer. Embodiments include forming a silicon oxynitride ARC on a polycrystalline silicon layer overlying a silicon oxide layer, depositing a thin undoped polycrystalline or amorphous silicon barrier layer on the ARC, forming a photoresist mask on the barrier layer, etching to form a gate electrode on a gate oxide layer and removing the photoresist mask. The undoped polycrystalline or amorphous silicon barrier layer is then removed employing conventional wet or dry etching techniques with high etch selectivity to the underlying gate oxide layer, thereby avoiding degradation of the gate oxide layer.

摘要翻译： 在ARC上形成未掺杂硅的薄阻挡层以防止抗蚀剂中毒和基底。 可以以相对于下面的栅极介电层的改进的产率和高选择性去除硅层，从而避免栅极电介质层的劣化。 实施例包括在覆盖氧化硅层的多晶硅层上形成氮氧化硅ARC，在ARC上沉积薄的未掺杂的多晶或非晶硅阻挡层，在阻挡层上形成光致抗蚀剂掩模，在栅极上形成栅极电极 氧化物层并去除光致抗蚀剂掩模。 然后使用对底层栅极氧化物层具有高蚀刻选择性的常规湿式或干式蚀刻技术去除未掺杂的多晶或非晶硅阻挡层，从而避免栅极氧化物层的劣化。

公开(公告)号：US06878622B1

公开(公告)日：2005-04-12

申请号：US10612554

申请日：2003-07-01

申请人： Wenge Yang ,  Ramkumar Subramanian ,  Fei Wang ,  Lewis Shen

发明人： Wenge Yang ,  Ramkumar Subramanian ,  Fei Wang ,  Lewis Shen

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/60 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC分类号： H01L21/76897 ,  H01L21/0276 ,  H01L21/31116 ,  H01L2924/3011

摘要： A method is provided for manufacturing a semiconductor device on a semiconductor substrate using a dielectric as a bottom anti-reflective coating for formation of a photoresist contact opening which is used to enlarge the Final Inspection Critical Dimension (FICD) of the conductive contact. A high selectivity etch is used to form a tapered contact.

摘要翻译： 提供了一种用于在半导体衬底上制造半导体器件的方法，该半导体衬底使用电介质作为用于形成光刻胶接触开口的底部抗反射涂层，用于扩大导电触点的最终检查临界尺寸（FICD）。 使用高选择性蚀刻来形成锥形接触。

公开(公告)号：US06534411B1

公开(公告)日：2003-03-18

申请号：US09548616

申请日：2000-04-13

申请人： Lewis Shen ,  Wenge Yang

发明人： Lewis Shen ,  Wenge Yang

IPC分类号： H01L21302

CPC分类号： H01L21/32137 ,  H01L21/31053

摘要： The high density plasma metal etch rate of a conductive material within a dense array of conductive lines is increased to greater than the etch rate of the conductive material in a bordering open field by controlling the source power and the bottom power in a plasma chamber, thereby reducing overetching, resist loss, and oxide loss in the open field, and facilitating planarization.

摘要翻译： 通过控制等离子体室中的源功率和底部功率，导电线路密集阵列内的导电材料的高密度等离子体金属蚀刻速率增加到大于接壤开放场中导电材料的蚀刻速率，由此 减少开放场中的过蚀刻，抗蚀损耗和氧化物损失，并促进平坦化。

公开(公告)号：US06372651B1

公开(公告)日：2002-04-16

申请号：US09286464

申请日：1999-04-06

申请人： Wenge Yang ,  Lewis Shen

发明人： Wenge Yang ,  Lewis Shen

IPC分类号： H01L213065

CPC分类号： H01L21/28273 ,  H01L21/0273 ,  H01L21/0276 ,  H01L21/0338 ,  H01L27/115

摘要： Memory gate stacks having widths of about 0.18 microns to 0.15 microns are formed by trimming a resist mask pattern, having line widths of about 0.25 microns, to a width of about 0.20 microns. An antireflective coating layer such as silicon oxynitride underlying the resist pattern is then etched to form etched silicon oxynitride pattern lines having widths of about 0.18 to 0.15 microns. The etched silicon oxynitride layer is then used for self-aligned etching of underlying layers to form the memory gate stack. Hence, a memory gate can be formed that has a width substantially less than the current photolithography limit during formation of the resist mask pattern.

摘要翻译： 通过将线宽约0.25微米的抗蚀剂掩模图案修剪到约0.20微米的宽度，形成具有约0.18微米至0.15微米宽度的存储器栅极叠层。 然后蚀刻抗蚀剂图案下方的抗氧化氮化硅等抗反射涂层，形成宽度为0.18〜0.15微米的蚀刻氮氧化硅图形线。 然后将蚀刻的氮氧化硅层用于底层的自对准蚀刻以形成存储器栅叠层。 因此，可以形成存储栅极，其在形成抗蚀剂掩模图案期间具有基本上小于当前光刻极限的宽度。

公开(公告)号：US06271154B1

公开(公告)日：2001-08-07

申请号：US09076661

申请日：1998-05-12

申请人： Lewis Shen ,  Wenge Yang

发明人： Lewis Shen ,  Wenge Yang

IPC分类号： H01L21302

CPC分类号： H01L21/31144 ,  G03F7/40 ,  H01L21/32139

摘要： A hard resist layer is formed on and/or within a deep-UV configured resist mask prior to patterning a semiconductor device feature. The hard resist layer reduces the amount of polymer residue generated during the patterning process, which can effect the resulting profile of the device feature. The hard resist mask is formed by either ion implantation or plasma treatments. Due to the formation of the hard resist layer, the thickness of the resist mask can be reduced, thereby increasing the resolution capabilities of the resist mask.

摘要翻译： 在图案化半导体器件特征之前，在深UV配置的抗蚀剂掩模之上和/或内部形成硬抗蚀剂层。 硬抗蚀剂层减少了在图案化过程期间产生的聚合物残余物的量，这可以影响器件特征的所得轮廓。 通过离子注入或等离子体处理形成硬质抗蚀剂掩模。 由于形成了抗蚀剂层，可以减小抗蚀剂掩模的厚度，从而提高抗蚀剂掩模的分辨能力。

公开(公告)号：US5702564A

公开(公告)日：1997-12-30

申请号：US368170

申请日：1995-01-03

申请人： Lewis Shen

发明人： Lewis Shen

IPC分类号： C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/3213 ,  H01L23/52

CPC分类号： H01L21/32136 ,  H01L21/32137

摘要： Undercutting of conductive lines in a dense array bordered by an open field is avoided by reducing the severity of etching when the conductive material in the open field is substantially removed. In a preferred embodiment, the flow rate of chlorine gas is reduced during high density chlorine plasma etching of a conductive pattern when the conductive material is substantially removed from the open field.

摘要翻译： 当开放场中的导电材料基本上被去除时，通过降低蚀刻的严重性来避免由开放场界定的致密阵列中的导电线的底切。 在优选实施例中，当导电材料基本上从开放场除去时，在导电图案的高密度氯等离子体蚀刻期间，氯气的流速减小。

公开(公告)号：US06452225B1

公开(公告)日：2002-09-17

申请号：US09617820

申请日：2000-07-17

申请人： Wenge Yang ,  Lewis Shen

发明人： Wenge Yang ,  Lewis Shen

IPC分类号： H01L29788

CPC分类号： H01L27/11517 ,  Y10S438/942 ,  Y10S438/95

摘要： A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.25 microns using conventional deep ultraviolet (DUV) photolithography techniques.

摘要翻译： 在形成存储器栅极期间，在氧氮化硅膜上形成厚度减小的抗蚀剂掩模图案。 抗蚀剂掩模图案具有足以在蚀刻氮氧化硅膜期间耐受去除的抗蚀剂厚度（3000至4000埃）。 基于抗蚀剂掩模图案蚀刻具有约800至1500埃厚度的氧氮化硅膜，然后用作掩模图案以蚀刻氮氧化硅层下面的多晶硅栅极层，以暴露部分隔离区域 相对于抗蚀剂掩模图案对准。 蚀刻后残留的抗蚀剂掩模的部分与蚀刻的氮氧化硅膜组合，具有足够的总厚度以用作沟道注入掩模。 使用具有减小的厚度的抗蚀剂掩模图案通过最小化不对准的发生来提高产率，并且使用常规的深紫外（DUV）光刻技术，可以在宽度小于0.25微米的掩模图案中可靠地形成空间。

公开(公告)号：US06355546B1

公开(公告)日：2002-03-12

申请号：US09371922

申请日：1999-08-11

申请人： Richard J. Huang ,  Lewis Shen

发明人： Richard J. Huang ,  Lewis Shen

IPC分类号： H01L213205

CPC分类号： H01L21/32139

摘要： A thermally grown oxide buffer layer is formed on a silicon layer prior to depositing an ARC thereon, thereby preventing damage to the silicon layer during ARC removal. Embodiments include thermally growing a silicon oxide buffer layer on an amorphous or polycrystalline silicon layer by thermal oxidation at a temperature of about 800° C. to about 900° C. in an atmosphere comprising oxygen or steam. A silicon oxynitride or silicon-rich silicon nitride ARC is then formed on the thermally grown protective silicon oxide buffer layer and a photoresist layer is formed on the ARC. The photoresist layer is patterned to form a mask and the underlying silicon layer etched to form a conductive feature, e.g., gate electrode. The photoresist mask is then removed and the ARC is stripped with hot phosphoric acid or by dry etching, while the thermally grown silicon oxide buffer layer protects the underlying silicon layer from damage.

摘要翻译： 在其上沉积ARC之前，在硅层上形成热生长的氧化物缓冲层，从而防止在ARC去除期间损坏硅层。 实施例包括通过在包含氧气或蒸气的气氛中在约800℃至约900℃的温度下热氧化在非晶或多晶硅层上热生长氧化硅缓冲层。 然后在热生长的保护性氧化硅缓冲层上形成氮氧化硅或富硅氮化物ARC，并在ARC上形成光致抗蚀剂层。 图案化光致抗蚀剂层以形成掩模，并且蚀刻底层硅层以形成导电特征，例如栅电极。 然后去除光致抗蚀剂掩模，并且用热磷酸或通过干蚀刻剥离ARC，而热生长的氧化硅缓冲层保护下面的硅层免受损坏。