公开(公告)号：US20100059817A1

公开(公告)日：2010-03-11

申请号：US12205438

申请日：2008-09-05

申请人： DANIEL PHAM ,  Bich-Yen Nguyen

发明人： DANIEL PHAM ,  Bich-Yen Nguyen

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/28105 ,  H01L29/42372

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

摘要翻译： 半导体器件包括第一导电类型和第一掺杂浓度的半导体层。 用作第一导电类型的漏极的第一半导体区域具有比半导体层更低的掺杂浓度，并且在半导体层之上。 栅极电介质在第一半导体区域之上。 栅极电介质上的栅极电极在中心部分的相对侧上具有含金属的中心部分和第一和第二硅部分。 用作第二导电类型的沟道的第二半导体区域具有在第一硅部分下面的第一部分和栅极电介质。 用作第一导电类型的源的第三半导体区域与第二半导体区域的第一部分横向相邻。 置换硅的含金属中心部分将源极增加到漏极击穿电压。

公开(公告)号：US20090321873A1

公开(公告)日：2009-12-31

申请号：US12470152

申请日：2009-05-21

申请人： Bich-Yen Nguyen ,  Carlos Mazure

发明人： Bich-Yen Nguyen ,  Carlos Mazure

IPC分类号： H01L27/12 ,  H01L21/20

CPC分类号： H01L21/76251

摘要： In one embodiment, the invention provides substrates that are structured so that devices fabricated in a top layer thereof have properties similar to the same devices fabricated in a standard high resistivity substrate. Substrates of the invention include a support having a standard resistivity, a semiconductor layer arranged on the support substrate having a high-resistivity, preferably greater than about 1000 Ohms-cm, an insulating layer arranged on the high-resistivity layer, and a top layer arranged on the insulating layer. The invention also provides methods for manufacturing such substrates.

摘要翻译： 在一个实施例中，本发明提供了被构造成使得在其顶层中制造的器件具有与在标准高电阻率衬底中制造的相同器件相似的性质的衬底。 本发明的基板包括具有标准电阻率的支撑体，布置在支撑基板上的具有高电阻率，优选地大于约1000欧姆 - 厘米的半导体层，设置在高电阻率层上的绝缘层，以及顶层 布置在绝缘层上。 本发明还提供了制造这种基底的方法。

公开(公告)号：US07538002B2

公开(公告)日：2009-05-26

申请号：US11361171

申请日：2006-02-24

申请人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

发明人： Da Zhang ,  Vance H. Adams ,  Bich-Yen Nguyen ,  Paul A. Grudowski

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/78654

摘要： A semiconductor fabrication process includes forming isolation structures on either side of a transistor region, forming a gate structure overlying the transistor region, removing source/drain regions to form source/drain recesses, removing portions of the isolation structures to form recessed isolation structures, and filling the source/drain recesses with a source/drain stressor such as an epitaxially formed semiconductor. A lower surface of the source/drain recess is preferably deeper than an upper surface of the recessed isolation structure by approximately 10 to 30 nm. Filling the source/drain recesses may precede or follow forming the recessed isolation structures. An ILD stressor is then deposited over the transistor region such that the ILD stressor is adjacent to sidewalls of the source/drain structure thereby coupling the ILD stressor to the source/drain stressor. The ILD stressor is preferably compressive or tensile silicon nitride and the source/drain structure is preferably silicon germanium or silicon carbon.

摘要翻译： 半导体制造工艺包括在晶体管区域的任一侧上形成隔离结构，形成覆盖晶体管区域的栅极结构，去除源极/漏极区域以形成源极/漏极凹部，去除隔离结构的部分以形成凹入的隔离结构;以及 用诸如外延形成的半导体的源极/漏极应力源填充源/漏极凹部。 源极/漏极凹部的下表面优选比凹入的隔离结构的上表面深大约10至30nm。 填充源极/漏极凹部可以在形成凹入的隔离结构之前或之后。 然后将ILD应激源沉积在晶体管区域上，使得ILD应力源与源极/漏极结构的侧壁相邻，从而将ILD应激源耦合到源极/漏极应力源。 ILD应力器优选为压缩或拉伸氮化硅，并且源极/漏极结构优选为硅锗或硅碳。

公开(公告)号：US07494856B2

公开(公告)日：2009-02-24

申请号：US11393340

申请日：2006-03-30

申请人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/76254 ,  H01L21/76283 ,  H01L29/66772 ,  H01L29/78684

摘要： A semiconductor fabrication process includes forming an etch stop layer (ESL) overlying a buried oxide (BOX) layer and an active semiconductor layer overlying the ESL. A gate electrode is formed overlying the active semiconductor layer. Source/drain regions of the active semiconductor layer are etched to expose the ESL. Source/drain stressors are formed on the ESL where the source/drain stressors strain the transistor channel. Forming the ESL may include epitaxially growing a silicon germanium ESL having a thickness of approximately 30 nm or less. Preferably a ratio of the active semiconductor layer etch rate to the ESL etch rate exceeds 10:1. A wet etch using a solution of NH4OH:H2O heated to a temperature of approximately 75° C. may be used to etch the source/drain regions. The ESL may be silicon germanium having a first percentage of germanium. The source/drain stressors may be silicon germanium having a second percentage of germanium for P-type transistors, and they may be silicon carbon for N-type transistors.

摘要翻译： 半导体制造工艺包括形成覆盖掩埋氧化物（BOX）层和覆盖ESL的有源半导体层的蚀刻停止层（ESL）。 形成覆盖有源半导体层的栅电极。 蚀刻有源半导体层的源极/漏极区域以露出ESL。 源极/漏极应力源在ESL上形成，其源极/漏极应力应变应变晶体管沟道。 形成ESL可以包括外延生长厚度为约30nm或更小的硅锗ESL。 优选地，有源半导体层蚀刻速率与ESL蚀刻速率的比率超过10:1。 可以使用加热至约75℃温度的NH 4 OH:H 2溶液进行湿式蚀刻来蚀刻源极/漏极区域。 ESL可以是具有第一百分比的锗的硅锗。 源极/漏极应力源可以是对于P型晶体管具有第二百分比的锗的硅锗，并且它们可以是N型晶体管的硅碳。

公开(公告)号：US20080296620A1

公开(公告)日：2008-12-04

申请号：US12174357

申请日：2008-07-16

申请人： Da Zhang ,  Bich-Yen Nguyen

发明人： Da Zhang ,  Bich-Yen Nguyen

IPC分类号： H01L29/778 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/4908 ,  H01L29/66507 ,  H01L29/66795 ,  H01L29/78684

摘要： An electronic device can include a semiconductor fin overlying an insulating layer. The electronic device can also include a semiconductor layer overlying the semiconductor fin. The semiconductor layer can have a first portion and a second portion that are spaced-apart from each other. In one aspect, the electronic device can include a conductive member that lies between and spaced-apart from the first and second portions of the semiconductor layer. The electronic device can also include a metal-semiconductor layer overlying the semiconductor layer. In another aspect, the semiconductor layer can abut the semiconductor fin and include a dopant. In a further aspect, a process of forming the electronic device can include reacting a metal-containing layer and a semiconductor layer to form a metal-semiconductor layer. In another aspect, a process can include forming a semiconductor layer, including a dopant, abutting a wall surface of a semiconductor fin.

摘要翻译： 电子器件可以包括覆盖绝缘层的半导体鳍片。 电子器件还可以包括覆盖半导体鳍片的半导体层。 半导体层可以具有彼此间隔开的第一部分和第二部分。 在一个方面，电子设备可以包括位于半导体层的第一和第二部分之间并与之隔开的导电构件。 电子器件还可以包括覆盖半导体层的金属 - 半导体层。 在另一方面，半导体层可以邻接半导体鳍并包括掺杂剂。 在另一方面，形成电子器件的方法可以包括使含金属层和半导体层反应以形成金属 - 半导体层。 在另一方面，一种方法可以包括形成邻接半导体鳍片的壁表面的包括掺杂剂的半导体层。

公开(公告)号：US20080268587A1

公开(公告)日：2008-10-30

申请号：US11742081

申请日：2007-04-30

申请人： Mariam G. Sadaka ,  Debby Eades ,  Joe Mogab ,  Bich-Yen Nguyen ,  Melissa O. Zavala ,  Gregory S. Spencer

发明人： Mariam G. Sadaka ,  Debby Eades ,  Joe Mogab ,  Bich-Yen Nguyen ,  Melissa O. Zavala ,  Gregory S. Spencer

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807

摘要： A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.

摘要翻译： 半导体工艺和装置通过使用反斜率分离技术蚀刻沉积的氧化物层（62）来形成具有混合或双衬底的高性能CMOS器件（108,109），以形成锥形隔离区域（76）并暴露下面的半导体层 ，42）在外延生长具有不同表面取向的第一和第二衬底（84,82）之前的体晶片结构中，其可以用单个CMP工艺进行平面化。 通过在通过外延生长（100）硅并在第二衬底（82）上形成第二栅极（103）形成的第一衬底（84）上形成第一栅电极（104），所述第二衬底（82）通过外延生长（110）硅 ，获得了包括具有改善的空穴迁移率的高k金属PMOS栅电极的高性能CMOS器件。

公开(公告)号：US07354814B2

公开(公告)日：2008-04-08

申请号：US10949057

申请日：2004-09-23

申请人： Marius K. Orlowski ,  Bich-Yen Nguyen

发明人： Marius K. Orlowski ,  Bich-Yen Nguyen

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/823807 ,  H01L21/823885 ,  H01L27/0922 ,  H01L29/78642 ,  H01L29/78687

摘要： A semiconductor fabrication process includes forming a recess in a semiconductor substrate. A silicon germanium film is formed on a sidewall of the recess. A gate dielectric and gate electrode are formed adjacent the silicon germanium film. Source/drain regions are then formed wherein a first source/drain region is adjacent a first side of the gate electrode in an upper surface of the substrate and a second source/drain region adjacent a second side of the gate electrode is below a lower surface of the recess. Etching the exposed portion of the substrate may be done so as to form a rounded corner at the junction of the recess sidewall and the recess lower surface. The silicon germanium film formation is preferably epitaxial. An epitaxial silicon film may be formed adjacent the silicon germanium film.

摘要翻译： 半导体制造工艺包括在半导体衬底中形成凹部。 在该凹槽的侧壁上形成硅锗膜。 在硅锗膜附近形成栅极电介质和栅电极。 然后形成源极/漏极区，其中第一源极/漏极区在衬底的上表面中与栅电极的第一侧相邻，并且与栅电极的第二侧相邻的第二源极/漏极区在下表面 的凹陷。 可以对衬底的暴露部分进行蚀刻，以便在凹陷侧壁和凹陷下表面的接合处形成圆角。 硅锗膜的形成优选是外延的。 可以在硅锗膜附近形成外延硅膜。

公开(公告)号：US20080020515A1

公开(公告)日：2008-01-24

申请号：US11458902

申请日：2006-07-20

申请人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

发明人： Ted R. White ,  Leo Mathew ,  Bich-Yen Nguyen ,  Zhonghai Shi ,  Voon-Yew Thean ,  Mariam G. Sadaka

IPC分类号： H01L21/00

CPC分类号： H01L21/845 ,  H01L21/76264 ,  H01L27/1203 ,  H01L27/1207 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A semiconductor process and apparatus provide a dual or hybrid substrate by forming a second semiconductor layer (214) that is isolated from, and crystallographically rotated with respect to, an underlying first semiconductor layer (212) by a buried insulator layer (213); forming an STI region (218) in the second semiconductor layer (214) and buried insulator layer (213); exposing the first semiconductor layer (212) in a first area (219) of a STI region (218); epitaxially growing a first epitaxial semiconductor layer (220) from the exposed first semiconductor layer (212); and selectively etching the first epitaxial semiconductor layer (220) and the second semiconductor layer (214) to form CMOS FinFET channel regions (e.g, 223) and planar channel regions (e.g., 224) from the first epitaxial semiconductor layer (220) and the second semiconductor layer (214).

摘要翻译： 半导体工艺和装置通过形成第二半导体层（214）提供双或混合衬底，所述第二半导体层通过掩埋绝缘体层与基底第一半导体层隔离并且相对于下面的第一半导体层进行晶体学旋转; 在第二半导体层（214）和掩埋绝缘体层（213）中形成STI区（218）; 在STI区域（218）的第一区域（219）中暴露所述第一半导体层（212）; 从所述暴露的第一半导体层（212）外延生长第一外延半导体层（220）; 以及选择性地蚀刻所述第一外延半导体层（220）和所述第二半导体层（214）以形成来自所述第一外延半导体层（220）的CMOS FinFET沟道区域（例如，223）和平面沟道区域（例如，224） 第二半导体层（214）。

公开(公告)号：US20070281436A1

公开(公告)日：2007-12-06

申请号：US11443628

申请日：2006-05-31

申请人： Mariam G. Sadaka ,  Ted R. White ,  Bich-Yen Nguyen

发明人： Mariam G. Sadaka ,  Ted R. White ,  Bich-Yen Nguyen

IPC分类号： H01L21/76

CPC分类号： H01L21/823878 ,  H01L21/823807 ,  H01L21/84

摘要： A semiconductor process and apparatus provide a shallow trench isolation region (96) with a trench liner (95, 104) for use in a hybrid substrate device (21) by lining a first trench with a first trench liner (95), and then lining a second trench formed within the first trench by depositing a second trench liner (104) that is anisotropically etched to expose an underlying substrate (70) on which is epitaxially grown a silicon layer (110) to fill the second trench. By forming first gate electrodes (251) over a first SOI substrate (90) using deposited (100) silicon and forming second gate electrodes (261) over an epitaxially grown (110) silicon substrate (110), a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes (261) having improved hole mobility.

摘要翻译： 半导体工艺和装置提供具有沟槽衬垫（95,104）的浅沟槽隔离区（96），用于混合衬底器件（21），用于通过用第一沟槽衬垫（95）衬里第一沟槽，然后衬里 通过沉积第二沟槽衬垫（104）形成第一沟槽内的第二沟槽，所述第二沟槽衬垫（104）被各向异性蚀刻以暴露其上外延生长硅衬底（110）以填充第二沟槽的下面的衬底（70）。 通过使用沉积的（100）硅并在外延生长（110）硅衬底（110）上形成第二栅电极（261）在第一SOI衬底（90）上形成第一栅电极（251），获得高性能CMOS器件 其包括具有改善的空穴迁移率的高k金属PMOS栅电极（261）。

公开(公告)号：US20070272952A1

公开(公告)日：2007-11-29

申请号：US11836844

申请日：2007-08-10

申请人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

发明人： Voon-Yew Thean ,  Brian Goolsby ,  Linda McCormick ,  Bich-Yen Nguyen ,  Colita Parker ,  Mariam Sadaka ,  Victor Vartanian ,  Ted White ,  Melissa Zavala

IPC分类号： H01L29/80

CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823878 ,  H01L27/1203

摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

摘要翻译： 电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。 在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。 在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。 可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。 可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。 在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。