公开(公告)号：US10276430B2

公开(公告)日：2019-04-30

申请号：US15119289

申请日：2015-04-29

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Zhiyong Wang ,  Dejin Wang ,  Jingjing Ma

IPC: H01L27/12 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02

Abstract: Provided is an intermetallic dielectric layer structure of a silicon-on-insulator device, comprising a silicon-rich oxide layer (54) covering a metal interconnect, a fluorine-silicon glass layer on the silicon-rich oxide layer, and a non-doped silicate glass layer on the fluorine-silicon glass layer; the thickness of the silicon-rich oxide layer (54) is 700 angstroms ±10%; the silicon-rich oxide layer having a greater thickness captures movable ions on an unsaturated bond, such that it is difficult for the movable ions to pass through the silicon-rich oxide layer, thus blocking the movable ions. The present invention has good performance in an integrity evaluation of the gate oxide layer, and avoids damage to the device caused by the aggregation of movable ions at an interface. Also provided are a silicon-on-insulator device and a method of manufacturing the intermetallic dielectric layer of the silicon-on-insulator device.

公开(公告)号：US10096699B2

公开(公告)日：2018-10-09

申请号：US14392251

申请日：2014-06-05

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shuo Zhang ,  Qiang Rui ,  Genyi Wang ,  Xiaoshe Deng

IPC: H01L29/73 ,  H01L21/02 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L21/324 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

Abstract: A field-stop reverse conducting insulated gate bipolar transistor and a manufacturing method therefor. The transistor comprises a terminal structure (200) and an active region (100). An underlayment of the field-stop reverse conducting insulated gate bipolar transistor is an N-type underlayment, the back surface of the underlayment is provided with an N-type electric field stop layer (1), one surface of the electric field stop layer departing from the underlayment is provided with a back-surface P-type structure (10), and the surface of the back-surface P-type structure is provided with a back-surface metal layer (12). A plurality of notches (11) which penetrate through the back-surface P-type structure (10) from the back-surface metal layer (12) to the electric field stop layer (1) are formed in the active region (100), and metals of the back-surface metal layer (12) are filled into the notches (11) to form a metal structure which extends into the electric field stop layer (1).

公开(公告)号：US10084073B2

公开(公告)日：2018-09-25

申请号：US15537753

申请日：2015-09-28

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Shukun Qi

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/739 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/225 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/762 ,  H01L21/324

CPC classification number: H01L29/7394 ,  H01L21/02236 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/7624 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66325

Abstract: Provided is a lateral insulated-gate bipolar transistor (LIGBT), comprising a substrate (10), an anode terminal and a cathode terminal on the substrate (10), and a drift region (30) and a gate (61) located between the anode terminal and the cathode terminal. The anode terminal comprises a P-type buried layer (52) on the substrate (10), an N-type buffer region (54) on the P-type buried layer (52), and a P+ collector region (56) on the surface of the N-type buffer region (54). The LIGBT further comprises a trench gate adjacent to the anode terminal, wherein the trench gate penetrates from the surfaces of the N-type buffer region (54) and the P+ collector region (56) to the P-type buried layer (52), and the trench gate comprises an oxidation layer (51) on the inner surface of a trench and polysilicon (53) filled into the oxidation layer.

公开(公告)号：US10003890B2

公开(公告)日：2018-06-19

申请号：US15119878

申请日：2015-06-25

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Yonggang Hu

IPC: H04R19/04 ,  H04R7/14 ,  H04R7/12 ,  B81B3/00 ,  H04R7/16

CPC classification number: H04R19/04 ,  B81B3/0037 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  G01L9/0045 ,  G01L9/0073 ,  H04R7/12 ,  H04R7/14 ,  H04R7/16 ,  H04R19/005 ,  H04R2201/003

Abstract: A MEMS microphone includes a substrate (100), a supporting part (200), an upper polar plate (300) and a lower polar plate (400). The substrate (100) is provided with an opening (120) penetrating the middle thereof; the lower polar plate (400) straddles the opening (120); the supporting part (200) is fixed on the lower polar plate (400); the upper polar plate (300) is affixed to the supporting part (200); an accommodating cavity (500) is formed among the supporting part (200), the upper polar plate (300) and the lower polar plate (400); a recess (600) opposite to the accommodating cavity (500) is arranged in an intermediate region of at least one of the upper polar plate (300) and the lower polar plate (400), and insulation is achieved between the upper polar plate (300) and a lower polar plate (400).

公开(公告)号：US09975766B2

公开(公告)日：2018-05-22

申请号：US15312146

申请日：2015-05-05

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Yonggang Hu ,  Guoping Zhou

IPC: B81C1/00

CPC classification number: B81C1/00619 ,  B81C1/00 ,  B81C2201/0133 ,  B81C2201/0142

Abstract: An MEMS-based method for manufacturing a sensor comprises the steps of: forming a shallow channel (120) and a support beam (140) on a front surface of a substrate (100); forming a first epitaxial layer (200) on the front surface of the substrate (100) to seal the shallow channel (120); forming a suspended mesh structure (160) below the first epitaxial layer (200); and forming a deep channel (180) at a position on a back surface of the substrate (100) corresponding to the shallow channel (120), so that the shallow channel (120) is in communication with the deep channel (180). In the Method of manufacturing a MEMS-based sensor, when a shallow channel is formed on a front surface, a support beam of a mass block is formed, so the etching of a channel is easier to control, the process is more precise, and the uniformity and the homogeneity of the formed support beam are better.

公开(公告)号：US09939724B2

公开(公告)日：2018-04-10

申请号：US14435945

申请日：2013-09-03

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Jiale Su

IPC: G03F1/38 ,  G03F7/20

CPC classification number: G03F7/2035 ,  G03F1/38 ,  G03F7/203

Abstract: A photolithography method and system based on a high step slope are provided. The method includes: S1, manufacturing a sacrificial layer with a high step slope on a substrate; S2, adopting a spin-on PR coating process to cover the sacrificial layer with a photoresist layer to form a photolithographic layer; S3, forming a mask pattern and a compensation pattern on a mask; and S4, performing photolithography processes, by a photolithography machine, on the photolithographic layer. By forming a slope-top compensation pattern and a slope compensation pattern on a mask to perform photolithography on the substrate of a sacrificial layer, a relatively wide compensation pattern is set in a part of the top of the slope with a small thickness, thereby compensating the overexposure at the top of the slope, reducing the error in the photolithographic pattern, and improving the precision of photolithography of the high step slope.

公开(公告)号：US09862595B2

公开(公告)日：2018-01-09

申请号：US15023057

申请日：2014-12-04

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Errong Jing

IPC: H01L21/30 ,  H01L21/46 ,  B81C1/00

CPC classification number: B81C1/00142 ,  B81C2201/0108 ,  B81C2201/0109 ,  B81C2201/013

Abstract: A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam pattern and a final dielectric film layer, wherein the final dielectric film layer serves as a support film of the final support beam pattern and the final non-support beam pattern; and removing the sacrificial layer.

公开(公告)号：US09728472B2

公开(公告)日：2017-08-08

申请号：US14435955

申请日：2013-12-31

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Anna Zhang ,  Xiaoming Li

IPC: H01L21/3065 ,  H01L21/66 ,  H01L21/683

CPC classification number: H01L22/26 ,  H01L21/3065 ,  H01L21/6831

Abstract: A method for wafer etching in a deep silicon trench etching process includes the following steps: a. electrostatically absorbing a wafer using an electrostatic chuck, and stabilizing the atmosphere required by the process (S110); b. performing the sub-steps of a main process for the wafer, and the time for the sub-steps of the main process being shorter than the time required by the wafer main process; c. releasing the electrostatic adsorption of the electrostatic chuck on the wafer; d. determining whether the cumulative time of the sub-steps of the main process reaches a predetermined threshold or not, if so, performing the step e (S150), and if not, repeating the operations in the steps a to c (S140); and e. ending a wafer manufacturing process. The etching method avoids the wafer from continuous contact with the electrostatic chuck, reduces electrostatic accumulation on the surface of the wafer, and therefore solves the problem of resist reticulation on the surface of the wafer in the DSIE process.

公开(公告)号：US20170212539A1

公开(公告)日：2017-07-27

申请号：US15327916

申请日：2015-08-18

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Nan ZHANG ,  Jing ZHOU

IPC: G05F1/46 ,  G05F1/575 ,  G05F1/56

CPC classification number: G05F1/468 ,  G05F1/56 ,  G05F1/575

Abstract: A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the reference voltage determining module (300) controls an enablement of the error amplifier (200) according to whether the voltage reference source module (100) is completely started, the error amplifier (200) controls ON/OFF of the power transmission device (400) according to the reference voltage provided by the voltage reference source module (100) and a feedback voltage provided by the feedback module (500). A chip having the above low dropout linear regulator circuit and a electronic device having the above chip are provided.

公开(公告)号：US09716169B2

公开(公告)日：2017-07-25

申请号：US14902261

申请日：2014-08-15

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD.

Inventor： Feng Huang ,  Guipeng Sun ,  Guangtao Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7816 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/7835

Abstract: A lateral double diffused metal oxide semiconductor field-effect transistor includes semiconductor substrates, body regions positioned in the semiconductor substrates, drift regions positioned in the semiconductor substrates, source regions and a body leading-out region which are positioned in the body regions and spaced from the drift regions, a field region and drain regions which are positioned in the drift regions, and gates positioned on the surfaces of the semiconductor substrates to partially cover the body regions, the drift regions and the field region, wherein the field region is of a finger-like structure and comprises a plurality of strip field regions which extend from the source regions to the drain regions and are isolated by the active regions; and the strip field regions provided with strip gate extending regions extending from the gates.