公开(公告)号：US06858495B2

公开(公告)日：2005-02-22

申请号：US10357427

申请日：2003-02-04

申请人： Erh-Kun Lai

发明人： Erh-Kun Lai

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit memory unit and fabrication method thereof. A semiconductor substrate forming a protruding semiconductor substrate is provided, an ion implantation region is formed on the semiconductor substrate beside the protruding semiconductor substrate, a spacer is formed on a sidewall of the protruding semiconductor substrate, a doped region is formed on the semiconductor substrate, and an ONO layer is conformally formed on the surface of the protruding semiconductor substrate, the spacer, the doped region, and the semiconductor substrate.

摘要翻译： 一种多位存储器单元及其制造方法。 提供了形成突出的半导体衬底的半导体衬底，在突出半导体衬底旁边的半导体衬底上形成离子注入区，在突出的半导体衬底的侧壁上形成间隔物，在半导体衬底上形成掺杂区， 并且在突出的半导体衬底，间隔物，掺杂区域和半导体衬底的表面上共形地形成ONO层。

公开(公告)号：US20050035388A1

公开(公告)日：2005-02-17

申请号：US10939385

申请日：2004-09-14

申请人： Erh-Kun Lai

发明人： Erh-Kun Lai

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792 ,  H01L27/108 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/7923

摘要： A multi-bit memory unit and fabrication method thereof. A semiconductor substrate forming a protruding semiconductor substrate is provided, an ion implantation region is formed on the semiconductor substrate beside the protruding semiconductor substrate, a spacer is formed on a sidewall of the protruding semiconductor substrate, a doped region is formed on the semiconductor substrate, and an ONO layer is conformally formed on the surface of the protruding semiconductor substrate, the spacer, the doped region, and the semiconductor substrate.

公开(公告)号：US06828197B1

公开(公告)日：2004-12-07

申请号：US10797042

申请日：2004-03-11

申请人： Erh-Kun Lai

发明人： Erh-Kun Lai

IPC分类号： H01L218246

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method for fabricating a nitride read-only memory. The memory region is integrated with a peripheral circuit region, with a polysilicon layer acting as word line in the memory region to serve as an insulator polishing stop layer with the insulator formed in the first shallow trenches in the peripheral region by disposing an oxide layer, wherein the insulator is simultaneously formed between polysilicon structures in the memory array region to prevent semiconductor substrate reaction with metal such as cobalt during salicidation of the polysilicon, and the ONO layer formed on the sidewalls of the shallow trenches avoids STI corner recess and profile deformation during thermal process.

摘要翻译： 一种制造氮化物只读存储器的方法。 存储区域与外围电路区域集成，多晶硅层在存储区域中充当字线，以用作绝缘体抛光停止层，其中绝缘体通过设置氧化物层而形成在周边区域中的第一浅沟槽中， 其中所述绝缘体同时形成在所述存储器阵列区域中的多晶硅结构之间，以防止半导体衬底与金属（例如钴）在多晶硅的硫化反应期间反应，并且形成在浅沟槽的侧壁上的ONO层避免了STI拐角凹陷和形状变形 热处理。

公开(公告)号：US06723603B2

公开(公告)日：2004-04-20

申请号：US10183530

申请日：2002-06-28

申请人： Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

发明人： Chien-Hung Liu ,  Erh-Kun Lai ,  Shyi Shuh Pan ,  Shou Wei Huang ,  Ying Tzoo Chen

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/7887

摘要： The present invention provides a method utilizing the fabrication process of poly-Si spacers to build a flash memory with 2bit/cell. In the present invention, recessed poly-Si spacers are used to fabricate discontinuous floating gates below a control gate to build a flash memory with 2bit/cell. The present invention is characterized in that the fabrication process of poly-Si spacers is exploited to complete the fabrication process of floating gates in automatic alignment way without any extra mask process. Moreover, each memory cell in this flash memory can store two bits, hence increasing the memory capacity.

摘要翻译： 本发明提供了利用多晶硅间隔物的制造工艺来构建具有2bit / cell的闪速存储器的方法。 在本发明中，凹入的多晶硅间隔物用于制造控制栅极下面的不连续的浮动栅极以构建具有2bit / cell的闪速存储器。 本发明的特征在于，多晶硅间隔物的制造工艺被利用以完全以自动对准方式完成浮栅的制造工艺，而无需任何额外的掩模工艺。 此外，该闪速存储器中的每个存储单元可以存储两个位，从而增加存储器容量。

公开(公告)号：US06670672B1

公开(公告)日：2003-12-30

申请号：US10175839

申请日：2002-06-21

申请人： Kent Kuohua Chang ,  Erh-Kun Lai

发明人： Kent Kuohua Chang ,  Erh-Kun Lai

IPC分类号： H01L29792

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792

摘要： A discrete NROM cell, at least comprising: a substrate; a first ON stacking gate and a second ON stacking gate over the substrate, wherein the ON stacking gate is a structure having a nitride layer over a bottom oxide layer; an oxide layer formed over the substrate covering the first and second ON stacking gate; a polysilicon layer formed over the oxide layer; and the source/drain implanted in the substrate and next to the ON stacking gates. The structure of discrete NROM cell of the invention can solve the problem of the electrons being trapped in the nitride layer of NROM cell, and also control the source/drain implant and ON structure at precisely symmetrical positions.

摘要翻译： 一个离散的NROM电池，至少包括：一个衬底; 在所述衬底上的第一ON堆叠栅极和第二ON堆叠栅极，其中所述ON堆叠栅极是在底部氧化物层上方具有氮化物层的结构; 形成在所述基板上的覆盖所述第一和第二ON堆叠栅极的氧化物层; 形成在所述氧化物层上的多晶硅层; 并且注入到衬底中并且靠近ON堆叠栅极的源极/漏极。 本发明的离散NROM电池的结构可以解决电子被捕获在NROM电池的氮化物层中的问题，并且还可以在精确对称的位置控制源极/漏极注入和ON结构。

公开(公告)号：US06413815B1

公开(公告)日：2002-07-02

申请号：US09682069

申请日：2001-07-17

申请人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

发明人： Erh-Kun Lai ,  Shyi-Shuh Pan ,  Chien-Hung Liu ,  Shou-Wei Huang ,  Ying-Tso Chen

IPC分类号： H01L218242

CPC分类号： H01L21/76808 ,  H01L23/5223 ,  H01L23/53238 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of simultaneously forming a dual damascence runner and a metal-insulator-metal (MIM) capacitor on a semiconductor wafer. The semiconductor wafer has a first dielectric layer, which has at least a first conductive layer and at least a bottom electrode of the MIM capacitor. The surfaces of the first conductive layer and the bottom electrode of the MIM capacitor are covered with a barrier layer. A second dielectric layer, a stop layer and a third dielectric layer are formed on the surface of the barrier layer and form a sandwiched structure. A first photoresist layer is formed and the third dielectric layer is anisotropically etched down to the stop layer, thus forming a trench and an opening in the third dielectric layer above the conductive layer and the bottom electrode of the MIM capacitor. A second photoresist layer is formed and the stop layer and the second dielectric layer are etched at a bottom of the opening down to the surface of the barrier layer so as to form an opening of the top electrode. A third photoresist layer is formed and the stop layer, the second dielectric layer and the barrier layer are etched through the contact opening down to the surface of the first conductive layer so as to form a contact hole.

摘要翻译： 一种在半导体晶片上同时形成双重阻力流道和金属 - 绝缘体 - 金属（MIM）电容器的方法。 半导体晶片具有至少具有MIM电容器的第一导电层和至少底部电极的第一电介质层。 MIM电容器的第一导电层和底部电极的表面被阻挡层覆盖。 在阻挡层的表面上形成第二电介质层，阻挡层和第三电介质层，并形成夹层结构。 形成第一光致抗蚀剂层，并且将第三介电层各向异性地向下蚀刻到停止层，从而在MIM电容器的导电层和底部电极上方的第三介电层中形成沟槽和开口。 形成第二光致抗蚀剂层，并且将阻止层和第二介电层在开口的底部蚀刻到阻挡层的表面，以形成顶部电极的开口。 形成第三光致抗蚀剂层，并且通过接触开口将停止层，第二介电层和阻挡层蚀刻到第一导电层的表面，以形成接触孔。

公开(公告)号：US06383903B1

公开(公告)日：2002-05-07

申请号：US09918638

申请日：2001-08-01

申请人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Hsin-Huei Chen ,  Ying-Tso Chen ,  Shou-Wei Hwang ,  Yu-Ping Huang

IPC分类号： H01L213205

CPC分类号： H01L27/105 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/1052

摘要： This invention relates to a method for forming the salicide, more particularly, to the method for forming the salicide in the partial region. The present invention uses an oxide layer to be the mask layer to form the salicide in the partial region of the logic circuit. The silicide is formed on the gate and is not formed in the diffusion region, which are in the cell array region. The silicide is formed on the gate and in the diffusion region, which are in the periphery region. The present invention method can make the semiconductor device obtain lower resistance and decrease the leakage defects.

摘要翻译： 本发明涉及一种形成硅化物的方法，更具体地说涉及在部分区域中形成硅化物的方法。 本发明使用氧化物层作为掩模层，在逻辑电路的部分区域中形成硅化物。 硅化物形成在栅极上并且不形成在电池阵列区域中的扩散区域中。 硅化物形成在栅极和位于周边区域的扩散区域中。 本发明的方法可以使半导体器件获得较低的电阻并降低漏电缺陷。

公开(公告)号：US06355539B1

公开(公告)日：2002-03-12

申请号：US09849245

申请日：2001-05-07

申请人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

发明人： Erh-Kun Lai ,  Shou-Wei Huang ,  Yu-Ping Huang

IPC分类号： H01L2176

CPC分类号： H01L21/76232

摘要： A method for forming a shallow trench isolation is disclosed. The method avoids using any silicon nitride material to prevent the kooi effect and use spacers to protect the corner portions of the STI. A conductive layer is used to replace the conventional used silicon nitride layer in the formation of conventional STI regions. The invention also uses a dielectric layer comprising a pad oxide layer as a sacrificial oxide layer so that an additional sacrificial oxide layer is no longer needed. The conductive layer will be oxidized together with the substrate in the formation of the gate oxide layer so that the isolation quality will not be degraded.

摘要翻译： 公开了一种用于形成浅沟槽隔离的方法。 该方法避免使用任何氮化硅材料来防止kooi效应并使用间隔物来保护STI的拐角部分。 在传统的STI区域的形成中，使用导电层代替常规使用的氮化硅层。 本发明还使用包括衬垫氧化物层作为牺牲氧化物层的电介质层，使得不再需要额外的牺牲氧化物层。 在形成栅极氧化物层时，导电层将与衬底一起被氧化，使得隔离质量不会降低。

公开(公告)号：US09019771B2

公开(公告)日：2015-04-28

申请号：US13661723

申请日：2012-10-26

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih ,  Erh-Kun Lai ,  Ming-Hsiu Lee

IPC分类号： G11C16/06 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0475 ,  G11C16/10

摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

摘要翻译： 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US08846549B2

公开(公告)日：2014-09-30

申请号：US11235786

申请日：2005-09-27

申请人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

发明人： Yen-Hao Shih ,  Hang-Ting Lue ,  Erh-Kun Lai ,  Kuang Yeu Hsieh

IPC分类号： H01L21/31 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51

CPC分类号： H01L21/28282 ,  G11C16/0466 ,  H01L29/513

摘要： A non-volatile memory device on a semiconductor substrate may include a bottom oxide layer over the substrate, a middle layer of silicon nitride over the bottom oxide layer, and a top oxide layer over the middle layer. The bottom oxide layer may have a hydrogen concentration of up to 5E19 cm−3 and an interface trap density of up to 5E11 cm−2 eV−1. The three-layer structure may be a charge-trapping structure for the memory device, and the memory device may further include a gate over the structure and source and drain regions in the substrate.

摘要翻译： 半导体衬底上的非易失性存储器件可以包括衬底上的底部氧化物层，底部氧化物层上的中间氮化硅层和中间层上的顶部氧化物层。 底部氧化物层可以具有高达5E19cm-3的氢浓度和高达5E11cm-2eV-1的界面陷阱密度。 三层结构可以是用于存储器件的电荷捕获结构，并且存储器件还可以包括在结构上的栅极和衬底中的源极和漏极区域。