公开(公告)号：US20210184059A1

公开(公告)日：2021-06-17

申请号：US16716419

申请日：2019-12-16

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： LANXIANG WANG ,  ENG HUAT TOH ,  SHYUE SENG TAN ,  KIOK BOONE ELGIN QUEK

IPC: H01L31/02 ,  H01L31/107 ,  H01L45/00 ,  H01L31/18

Abstract: A sensor is provided, which includes a semiconductor substrate, a photodiode region, and a multi-layered resistive element. The photodiode region is arranged in the semiconductor substrate. The multi-layered resistive element is arranged over the semiconductor substrate and is coupled with the photodiode region.

公开(公告)号：US20210164845A1

公开(公告)日：2021-06-03

申请号：US16700358

申请日：2019-12-02

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bin Liu ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: G01K7/01 ,  G11C11/406 ,  G11C7/04 ,  G11C11/4072

Abstract: Structures including non-volatile memory elements and methods of forming such structures. The structure includes a first non-volatile memory element, a second non-volatile memory element, and temperature sensing electronics coupled to the first non-volatile memory element and the second non-volatile memory element.

公开(公告)号：US20210159234A1

公开(公告)日：2021-05-27

申请号：US16695725

申请日：2019-11-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Xinshu Cai ,  Eng Huat Toh

IPC: H01L27/11519 ,  H01L27/11521

Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.

公开(公告)号：US11004972B2

公开(公告)日：2021-05-11

申请号：US16438574

申请日：2019-06-12

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Bo Yu ,  Shaoqiang Zhang

IPC: H01L29/78 ,  H01L27/12 ,  H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/786

Abstract: A device may include a semiconductor-on-insulator (SOI) structure that may include a substrate, an insulator layer over the substrate, and a semiconductor layer over the insulator layer. The semiconductor layer may include a first conductivity region and a second conductivity region at least partially arranged within the semiconductor layer. The device may further include a gate structure arranged over the semiconductor layer and between the first conductivity region and the second conductivity region; a first conductor element arranged through the semiconductor layer and the insulator layer of the SOI structure to electrically contact the substrate; a second conductor element arranged to electrically contact the gate structure; and a conducting member connecting the first conductor element and the second conductor element to electrically couple the first conductor element and the second conductor element.

公开(公告)号：US20210135101A1

公开(公告)日：2021-05-06

申请号：US16672632

申请日：2019-11-04

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat TOH ,  Shyue Seng TAN ,  Steven SOSS

IPC: H01L45/00

Abstract: A memory device may include at least one inert electrode, at least one active electrode, an insulating element arranged at least partially between the at least one active electrode and the at least one inert electrode, and a switching element arranged under the insulating element. The switching element may be arranged at least partially between the at least one active electrode and the at least one inert electrode. The switching element may include a first end and a second end contacting the at least one active electrode; and a middle segment between the first end and the second end, where the middle segment may at least partially contact the at least one inert electrode.

公开(公告)号：US10978510B2

公开(公告)日：2021-04-13

申请号：US16443255

申请日：2019-06-17

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Pinghui Li ,  Haiqing Zhou ,  Liying Zhang ,  Wanbing Yi ,  Ming Zhu ,  Danny Pak-Chum Shum ,  Darin Chan

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C5/02 ,  G11C11/16 ,  H01L27/02 ,  H01L43/12 ,  G11C11/15

Abstract: Methods of forming a MTJ dummy fill gradient across near-active-MRAM-cell periphery and far-outside-MRAM logic regions and the resulting device are provided. Embodiments include providing an embedded MRAM layout with near-active-MRAM-cell periphery logic and far-outside-MRAM logic regions; forming a MTJ structure within the layout based on minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first and second metal layers; forming a high-density MTJ dummy structure in the near-active-MRAM-cell periphery logic region based on second minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer; and forming a low-density MTJ dummy structure in the far-outside-MRAM logic region based on third minimum space and distance rules relative to a first metal layer, a second metal layer, and/or both the first metal layer and the second metal layer.

公开(公告)号：US20210082905A1

公开(公告)日：2021-03-18

申请号：US16574184

申请日：2019-09-18

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Jie ZENG ,  Raunak KUMAR ,  Kyong Jin HWANG

IPC: H01L27/02 ,  H01L29/735 ,  H01L27/092

Abstract: An ESD protection device may include a substrate, a first conductivity region arranged at least partially within the substrate, a second conductivity region arranged at least partially within the first conductivity region, third and fourth conductivity regions arranged at least partially within the second conductivity region, and first and second terminal portions arranged at least partially within the third and fourth conductivity regions respectively. The third and fourth conductivity regions may be spaced apart from each other. The substrate and the second conductivity region may have a first conductivity type. The first conductivity region, third conductivity region, fourth conductivity region and first and second terminal portions may have a second conductivity type different from the first conductivity type. The first and second terminal portions may have higher doping concentrations than the third and fourth conductivity regions respectively.

公开(公告)号：US20210043637A1

公开(公告)日：2021-02-11

申请号：US16532522

申请日：2019-08-06

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Desmond Jia Jun LOY ,  Eng Huat Toh ,  Bin Liu ,  Shyue Seng Tan

IPC: H01L27/112 ,  H01L29/36 ,  H01L21/265 ,  H01L21/266 ,  H01L21/762 ,  H01L23/525 ,  G11C17/16 ,  G11C17/18

Abstract: A memory device may include a first conductivity region, and second and third conductivity regions arranged at least partially within the first conductivity region. The first and second conductivity regions may have a different conductivity type from at least a part of the third conductivity region. The memory device may include first and second gates arranged over the third conductivity region. The second conductivity region may be coupled to a source line, and the gates may be coupled to respective word lines. When a predetermined write voltage difference is applied between the source line and a word line, an oxide layer of the gate coupled to the word line may break down to form a conductive link between the gate electrode of the gate and the third conductivity region. The memory device may have a smaller cell area, and may be capable of operating at both higher and lower voltages.

公开(公告)号：US10903272B2

公开(公告)日：2021-01-26

申请号：US16205314

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Eng Huat Toh

IPC: H01L27/24 ,  H01L45/00

Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.

公开(公告)号：US20210013405A1

公开(公告)日：2021-01-14

申请号：US16504344

申请日：2019-07-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： DAO HWEE GRAYSON WONG ,  KAZUTAKA YAMANE ,  JU DY LIM ,  DINGGUI ZENG ,  CHIM SENG SEET

IPC: H01L45/00

Abstract: The disclosure relates generally to resistive switching nonvolatile random access memory (ReRAM) devices, and more generally to structures and methods of fabricating multiple conductive elements in ReRAM devices. A resistive memory device is presented, the device comprising a first electrode having a first work function, and a second electrode having a second work function, the first work function being different from the second work function. A dielectric layer is disposed between the first and second electrodes. The device further comprises a set of nanocrystal structures distributed in the dielectric layer. A conductive layer is also disposed in the dielectric layer.