公开(公告)号：US20240105683A1

公开(公告)日：2024-03-28

申请号：US17955225

申请日：2022-09-28

Applicant: GlobalFoundries U.S. Inc.

Inventor： Vvss Satyasuresh Choppalli ,  Anupam Dutta ,  Rajendran Krishnasamy ,  Robert Gauthier, JR. ,  Xiang Xiang Lu ,  Anindya Nath

IPC: H01L25/07 ,  H01L21/77 ,  H01L23/14 ,  H01L23/522

CPC classification number: H01L25/072 ,  H01L21/77 ,  H01L23/147 ,  H01L23/5228

Abstract: Structures including multiple semiconductor devices and methods of forming same. The structure comprises a first device structure including a first well and a second well in a semiconductor substrate, a second device structure including a doped region in the semiconductor substrate, and a first high-resistivity region in the semiconductor substrate. The first well has a first conductivity type, the second well has a second conductivity type opposite to the first conductivity type, and the first well adjoins the second well to define a p-n junction. The doped region of the second device structure has the first conductivity type or the second conductivity type. The high-resistivity region has a higher electrical resistivity than the semiconductor substrate, and the high-resistivity region is positioned between the first device structure and the second device structure.

公开(公告)号：US20240103217A1

公开(公告)日：2024-03-28

申请号：US17953804

申请日：2022-09-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Brian McGowan ,  Ping-Chuan Wang ,  Oscar Restrepo

IPC: G02B6/122

CPC classification number: G02B6/122 ,  G02B2006/12142

Abstract: Structures for a thermo-optic phase shifter and methods of forming such structures. The structure comprises a waveguide structure including a waveguide core. The structure further comprises a silicide layer, a first dielectric layer arranged in a lateral direction between the silicide layer and the waveguide core, and a second dielectric layer positioned over the waveguide core, the silicide layer, and the first dielectric layer. The first dielectric layer comprises a first material having a first thermal conductivity, and the second dielectric layer comprises a second material having a second thermal conductivity that is less than the first thermal conductivity.

公开(公告)号：US20240097029A1

公开(公告)日：2024-03-21

申请号：US17933304

申请日：2022-09-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nan Wu

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/285 ,  H01L21/74 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L21/2252 ,  H01L21/28518 ,  H01L21/743 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/45 ,  H01L29/66484 ,  H01L29/6656

Abstract: Disclosed is a structure including a field effect transistor (FET). The FET includes, on an insulator layer above a substrate, source/drain regions and a section of a semiconductor layer extending laterally between the source/drain regions. A primary gate structure is made of the insulator layer and a well region in the substrate opposite at least the section of the semiconductor layer extending laterally between the source/drain regions. One or two secondary gate structures are on the semiconductor layer between and near one or both of the source/drain regions, respectively. The FET can further include a patterned conformal dielectric layer, which is on the center of the semiconductor layer between the source/drain regions, and which extends onto the secondary gate structure(s). Also disclosed are methods of operating the structure by biasing the secondary gate structure(s) to adjust the effective gate length of the FET and methods of forming the structure.

公开(公告)号：US11935928B2

公开(公告)日：2024-03-19

申请号：US17747476

申请日：2022-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hong Yu ,  Jianwei Peng ,  Vibhor Jain

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/737

CPC classification number: H01L29/41708 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/66242 ,  H01L29/7371

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a bipolar transistor with self-aligned asymmetric spacer and methods of manufacture. The structure includes: a base formed on a semiconductor substrate; an asymmetrical spacer surrounding the base; an emitter on a first side of the base and separated from the base by the asymmetrical spacer; and a collector on a second side of the base and separated from the base by the asymmetrical spacer.

公开(公告)号：US11934021B2

公开(公告)日：2024-03-19

申请号：US17649191

申请日：2022-01-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hemant Martand Dixit ,  William J. Taylor, Jr. ,  Yusheng Bian ,  Theodore Letavic ,  Oscar D. Restrepo

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

CPC classification number: G02B6/4269 ,  G02B6/122 ,  G02B6/125 ,  G02B2006/12135 ,  G02B2006/12142

Abstract: The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.

公开(公告)号：US20240088272A1

公开(公告)日：2024-03-14

申请号：US17931938

申请日：2022-09-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/735 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625

Abstract: Embodiments of the disclosure provide a bipolar transistor and gate structure on a semiconductor fin and methods to form the same. A structure according to the disclosure includes a semiconductor fin including an intrinsic base region and an extrinsic base region adjacent the intrinsic base region along a length of the semiconductor fin. Sidewalls of the intrinsic base region of the semiconductor fin are adjacent an emitter and a collector along a width of the semiconductor fin. A gate structure is on the semiconductor fin and between the intrinsic base region and the extrinsic base region.

公开(公告)号：US20240088157A1

公开(公告)日：2024-03-14

申请号：US17942233

申请日：2022-09-12

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Sarah McTaggart ,  Aaron Vallett ,  Rajendran Krishnasamy ,  Megan Lydon-Nuhfer

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/76286 ,  H01L21/84

Abstract: Semiconductor device structures with device isolation and methods of forming a semiconductor device structure with device isolation. The structure comprises a semiconductor substrate, a first semiconductor layer on the semiconductor substrate, a second semiconductor layer in a cavity in the first semiconductor layer, and a device structure including a doped region in the second semiconductor layer. The first semiconductor layer comprises a porous semiconductor material, and the second semiconductor layer comprises a single-crystal semiconductor material.

公开(公告)号：US20240085247A1

公开(公告)日：2024-03-14

申请号：US17931670

申请日：2022-09-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Santosh Sharma ,  Michael J. Zierak ,  Steven J. Bentley ,  Johnatan Avraham Kantarovsky

IPC: G01K7/18 ,  H01C7/04 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: G01K7/183 ,  H01C7/041 ,  H01L27/0605 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: A structure includes a negative temperature coefficient (NTC) resistor for use in gallium nitride (GaN) technology. The NTC resistor includes a p-type doped GaN (pGaN) layer, and a gallium nitride (GaN) heterojunction structure under the pGaN layer. The GaN heterojunction structure includes a barrier layer and a channel layer. An isolation region extends across an interface of the barrier layer and the channel layer, and a first metal electrode is on the pGaN layer spaced from a second metal electrode on the pGaN layer. The NTC resistor can be used as a temperature compensated reference in a structure providing a temperature detection circuit. The temperature detection circuit includes an enhancement mode HEMT sharing parts with the NTC resistor and includes temperature independent current sources including depletion mode HEMTs.

公开(公告)号：US11927801B2

公开(公告)日：2024-03-12

申请号：US17880006

申请日：2022-08-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian ,  Abdelsalam Aboketaf

IPC: G02B6/126 ,  G02B6/12 ,  G02B6/132

CPC classification number: G02B6/126 ,  G02B6/12002 ,  G02B6/132 ,  G02B2006/1215

Abstract: Structures for a waveguide core and methods of forming such structures. The structure comprises a stacked waveguide core including a first waveguide core and a second waveguide core stacked with the first waveguide core, and a layer adjacent to the stacked waveguide core. The layer comprises a material having a refractive index that is variable in response to a stimulus.

公开(公告)号：US11923417B2

公开(公告)日：2024-03-05

申请号：US17692517

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  Shesh Mani Pandey

IPC: H01L29/10 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/66 ,  H01L29/735 ,  H01L29/737

CPC classification number: H01L29/1008 ,  H01L29/6625 ,  H01L29/735 ,  H01L21/8222 ,  H01L27/082 ,  H01L29/737

Abstract: Structures for a bipolar junction transistor and methods of forming a structure for a bipolar junction transistor. The structure includes a substrate having a well, a first terminal including a first raised semiconductor layer, a second terminal including a second raised semiconductor layer, and a base layer positioned in a lateral direction between the first raised semiconductor layer of the first terminal and the second raised semiconductor layer of the second terminal. The base layer has an overlapping arrangement with the well. The structure further includes a dielectric layer positioned in a vertical direction between the first terminal and the substrate, the second terminal and the substrate, and the base layer and the substrate.