公开(公告)号：US11894845B1

公开(公告)日：2024-02-06

申请号：US17898937

申请日：2022-08-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H03K3/00 ,  H03K3/012 ,  H03K5/01 ,  H03K3/037 ,  H03K5/00

CPC classification number: H03K3/012 ,  H03K3/037 ,  H03K5/01 ,  H03K2005/00013

Abstract: Embodiments of the disclosure provide a structure and related method to delay data signals through a data path using a lockup latch driven by the inverse of a clock signal. A structure according to the disclosure provides a launch pulse latch coupled to a capture pulse latch through a data path. The data path includes a combinational logic for processing signals within the data path. An edge of a clock signal drives the launch pulse latch and the capture pulse latch. A lockup latch is within the data path between the launch pulse latch and the capture pulse latch. An inverse of the clock signal drives the lockup latch.

公开(公告)号：US11892680B2

公开(公告)日：2024-02-06

申请号：US17853186

申请日：2022-06-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

CPC classification number: G02B6/305 ,  G02B6/1228 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12121

Abstract: Structures for an edge coupler and methods of fabricating a structure for an edge coupler. The structure comprises an edge coupler including a first waveguide core and a second waveguide core. The first waveguide core is positioned in a vertical direction between the second waveguide core and a substrate. The first waveguide core has a first longitudinal axis, the second waveguide core has a second longitudinal axis, and the second longitudinal axis of the second waveguide core is slanted at an angle relative to the first longitudinal axis of the first waveguide core.

公开(公告)号：US20240035898A1

公开(公告)日：2024-02-01

申请号：US17874709

申请日：2022-07-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing ZHAO ,  Yiching CHEN ,  Oscar D. RESTREPO

IPC: G01K7/18 ,  H01L29/66

CPC classification number: G01K7/186 ,  H01L29/66825 ,  H01L29/66795

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to built-in temperature sensors and methods of manufacture. The structure includes: at least one active gate structure; and a built-in temperature sensor adjacent to and on a same device level as the at least one active gate structure, the built-in temperature sensor further includes force lines and sensing lines.

公开(公告)号：US20240030160A1

公开(公告)日：2024-01-25

申请号：US18479230

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: H01L23/00 ,  G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/564 ,  G06F30/392 ,  H01L23/66 ,  H03H1/0007 ,  H01L23/585

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US20240027685A1

公开(公告)日：2024-01-25

申请号：US17869858

申请日：2022-07-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Yusheng Bian

IPC: G02B6/125 ,  G02B6/136

CPC classification number: G02B6/125 ,  G02B6/136 ,  G02B2006/12119

Abstract: Structures for a waveguide crossing and methods of fabricating a structure for a waveguide crossing. The structure comprises a first waveguide core and a second waveguide core each including a first section, a second section, and a first waveguide bend connecting the first section to the second section. The second section terminates the first waveguide core. The second section terminates the second waveguide core. The second waveguide bend has a side surface that is spaced from a side surface of the first waveguide bend by a gap. A third waveguide core is terminated by a section having an overlapping arrangement with the second section of the first waveguide core. A fourth waveguide core is terminated by a section having an overlapping arrangement with the second section of the second waveguide core.

公开(公告)号：US11881241B2

公开(公告)日：2024-01-23

申请号：US17709525

申请日：2022-03-31

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan ,  Bipul C. Paul

IPC: G11C11/16 ,  G11C7/06

CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675

Abstract: A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.

公开(公告)号：US20240021713A1

公开(公告)日：2024-01-18

申请号：US18373598

申请日：2023-09-27

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Alexander Derrickson ,  Jagar Singh ,  Vibhor Jain ,  Andreas Knorr ,  Alexander Martin ,  Judson R. Holt ,  Zhenyu Hu

IPC: H01L29/735 ,  H01L29/66 ,  H01L29/737 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/735 ,  H01L29/6625 ,  H01L29/737 ,  H01L29/0808 ,  H01L29/41708 ,  H01L29/0821

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a lateral bipolar transistor and methods of manufacture. A structure includes: an intrinsic base comprising semiconductor material in a channel region of a semiconductor substrate; an extrinsic base vertically above the intrinsic base; a raised collector region on the semiconductor substrate and laterally connected to the intrinsic base; and a raised emitter region on the semiconductor substate and laterally connected to the intrinsic base.

公开(公告)号：US20240021243A1

公开(公告)日：2024-01-18

申请号：US17812485

申请日：2022-07-14

Applicant: GlobalFoundries U.S. Inc.

Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2213/79 ,  G11C2013/0054

Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

公开(公告)号：US11869958B2

公开(公告)日：2024-01-09

申请号：US17745280

申请日：2022-05-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Shesh Mani Pandey ,  Vibhor Jain

IPC: H01L29/737 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7371 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66242

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes: a collector in a semiconductor substrate; a subcollector in the semiconductor substrate; an intrinsic base over the subcollector; an extrinsic base adjacent to the intrinsic base; an emitter over the intrinsic base; and an isolation structure between the extrinsic base and the emitter and which overlaps the subcollector.

公开(公告)号：US11862511B2

公开(公告)日：2024-01-02

申请号：US17527716

申请日：2021-11-16

Applicant: GlobalFoundries U.S. Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli ,  Alvin Joseph

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L21/76297 ,  H01L21/02595

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. The structure includes a semiconductor substrate having a first trench, and a trench isolation region positioned in the first trench. The trench isolation region contains a dielectric material, the trench isolation region includes a second trench surrounded by the dielectric material, and the trench isolation region includes openings that penetrate through the dielectric material. A semiconductor layer is positioned in the second trench of the trench isolation region. The semiconductor layer contains a single-crystal semiconductor material.