公开(公告)号：US20070289769A1

公开(公告)日：2007-12-20

申请号：US11844164

申请日：2007-08-23

Applicant: Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

Inventor： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Yang-Ho Bae

IPC: H01B5/00

CPC classification number: H01L27/12 ,  H01L21/76838 ,  H01L23/5283 ,  H01L23/53209 ,  H01L29/4908 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: A multi-layer wiring for use with thin film transistors (TFTs), methods of manufacturing the multi-layer wiring, and TFTs employing the multi-layer wiring are provided. In one embodiment, the multi-layer wiring includes a main wiring and a sub-wiring on the main wiring. The main wiring includes a first metal and the sub-wiring includes an alloy wherein a majority of the alloy is the first metal. The multi-layer wiring can exhibit decreased electrical resistance and a reduced tendency to develop malfunctions such as hillocks or spiking. The multi-layer wiring can also exhibit improved contact characteristics with other conductive elements of TFT display devices.

Abstract translation: 提供了用于薄膜晶体管（TFT）的多层布线，多层布线的制造方法以及采用多层布线的TFT。 在一个实施例中，多层布线包括主布线和主布线上的副布线。 主配线包括第一金属，并且子布线包括其中大部分合金是第一金属的合金。 多层布线可以表现出降低的电阻和降低发展故障的倾向，如小丘或尖峰。 多层布线也可以表现出与TFT显示装置的其它导电元件的接触特性的改善。

公开(公告)号：US07301170B2

公开(公告)日：2007-11-27

申请号：US11180989

申请日：2005-07-12

Applicant: Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

Inventor： Beom-Seok Cho ,  Yang-Ho Bae ,  Je-Hun Lee ,  Chang-Oh Jeong

IPC: H01L29/04

CPC classification number: G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/3276 ,  Y10S438/924

Abstract: The present invention provides a TFT array panel and a manufacturing method of the same, which has signal lines including a lower layer of an Al containing metal and an upper layer of a molybdenum alloy (Mo-alloy) comprising molybdenum (Mo) and at least one of niobium (Nb), vanadium (V), and titanium (Ti). Accordingly, undercut, overhang, and mouse bites which may arise in an etching process, are prevented, and TFT array panels that have signal lines having low resistivity and good contact characteristics are provided.

Abstract translation: 本发明提供一种TFT阵列面板及其制造方法，其特征在于，具有含有Al的金属的下层和包含钼（Mo）的钼合金（Mo合金）的上层的信号线，至少包括 铌（Nb），钒（V）和钛（Ti）之一。 因此，防止在蚀刻工艺中可能出现的底切，突出和小鼠咬合，并且提供具有低电阻率和良好接触特性的信号线的TFT阵列面板。

公开(公告)号：US20070236641A1

公开(公告)日：2007-10-11

申请号：US11695751

申请日：2007-04-03

Applicant: Hong-Long NING ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Do-Hyun KIM ,  Sung-Hen CHO ,  Ki-Yong SONG ,  Chang-Ho NOH

Inventor： Hong-Long NING ,  Chang-Oh JEONG ,  Je-Hun LEE ,  Do-Hyun KIM ,  Sung-Hen CHO ,  Ki-Yong SONG ,  Chang-Ho NOH

IPC: G02F1/1343

CPC classification number: G02F1/136286 ,  G02F2001/13629 ,  G02F2001/136295

Abstract: A method of fabricating a thin film transistor (TFT) substrate includes forming a gate line and a data line on an insulating substrate. The data line crosses the gate line and is insulated from the gate line. The formation of the gate line, the data line, or both the gate line and the data line includes forming a low-resistive conductive pattern on a base pattern using an electroless plating method.

Abstract translation: 制造薄膜晶体管（TFT）基板的方法包括在绝缘基板上形成栅极线和数据线。 数据线与栅极线交叉并与栅极线绝缘。 栅极线，数据线或栅极线和数据线两者的形成包括使用化学镀方法在基底图案上形成低电阻导电图案。

公开(公告)号：US20070102770A1

公开(公告)日：2007-05-10

申请号：US11619451

申请日：2007-01-03

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: H01L29/76

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US20070013077A1

公开(公告)日：2007-01-18

申请号：US11474918

申请日：2006-06-24

Applicant: Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

Inventor： Je-hun Lee ,  Chang-oh Jeong ,  Beom-seok Cho ,  Yang-ho Bae

IPC: H01L23/48

CPC classification number: H01L29/4908 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L23/53238 ,  H01L27/12 ,  H01L27/124 ,  H01L29/458 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: Provided are a wire structure, a method of forming a wire, a thin film transistor (TFT) substrate, and a method of manufacturing the TFT substrate. The wire structure includes a barrier layer disposed on a lower structure, a copper conductive layer comprising copper or copper alloy disposed on the barrier layer, an intermediate layer comprising copper nitride disposed on the copper conductive layer, and a capping layer disposed on the intermediate layer.

Abstract translation: 提供一种线结构，形成线的方法，薄膜晶体管（TFT）基板以及制造TFT基板的方法。 导线结构包括设置在下部结构上的阻挡层，设置在阻挡层上的包含铜或铜合金的铜导电层，设置在铜导电层上的包含氮化铜的中间层和设置在中间层上的覆盖层 。

公开(公告)号：US20060091396A1

公开(公告)日：2006-05-04

申请号：US11249500

申请日：2005-10-14

Applicant: Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

Inventor： Je-Hun Lee ,  Yang-Ho Bae ,  Beom-Seok Cho ,  Chang-Oh Jeong

IPC: H01L29/04

CPC classification number: H01L27/3279 ,  H01L27/124 ,  H01L27/1288 ,  H01L51/0023 ,  H01L51/56

Abstract: The invention provides a thin film transistor (TFT) array panel that includes an insulating substrate; a gate line formed on the insulating substrate and having a first layer of an Al containing metal, a second layer of a Cu containing metal that is thicker than the first layer, and a gate electrode; a gate insulating layer arranged on the gate line; a semiconductor arranged on the gate insulating layer; a data line having a source electrode and arranged on the gate insulating layer and the semiconductor; a drain electrode arranged on the gate insulating layer and the semiconductor and facing the source electrode; a passivation layer having a contact hole and arranged on the data line and the drain electrode; and a pixel electrode arranged on the passivation layer and coupled with the drain electrode through the contact hole.

Abstract translation: 本发明提供一种薄膜晶体管（TFT）阵列面板，其包括绝缘基板; 形成在所述绝缘基板上并具有含有Al的金属的第一层，比所述第一层更厚的含Cu金属的第二层的栅极线和栅电极; 栅极绝缘层，布置在栅极线上; 布置在栅绝缘层上的半导体; 数据线，其具有源电极并且布置在所述栅极绝缘层和所述半导体上; 布置在所述栅绝缘层和所述半导体上并面对所述源电极的漏电极; 钝化层，其具有接触孔并且布置在所述数据线和所述漏电极上; 以及设置在钝化层上并通过接触孔与漏电极耦合的像素电极。

公开(公告)号：US20060076562A1

公开(公告)日：2006-04-13

申请号：US11215067

申请日：2005-08-29

Applicant: Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

Inventor： Je-Hun Lee ,  Beom-Seok Cho ,  Chang-Oh Jeong ,  Joo-Han Kim

IPC: H01L29/04 ,  H01L27/148

CPC classification number: H01L27/124 ,  H01L27/1288 ,  H01L29/12 ,  H01L29/458

Abstract: The present invention provides a thin film transistor array panel comprising: an insulating substrate; a gate line formed on the insulating substrate and having a gate electrode; a gate insulating layer formed on the gate line; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; diffusion barriers formed on the semiconductor and containing nitrogen; a data line crossing the gate line and having a source electrode partially contacting the diffusion barriers; a drain electrode partially contacting the diffusion barriers and facing the source electrode at on the gate electrode; and a pixel electrode electrically connected to the drain electrode.

Abstract translation: 本发明提供一种薄膜晶体管阵列板，包括：绝缘基板; 形成在所述绝缘基板上并具有栅电极的栅极线; 栅极绝缘层，形成在栅极线上; 形成在栅极绝缘层上并与栅电极重叠的半导体; 在半导体上形成并含有氮的扩散阻挡层; 跨越栅极线并且具有部分地接触扩散阻挡层的源电极的数据线; 漏电极部分地与扩散阻挡层接触并且与栅电极上的源电极相对; 以及电连接到漏电极的像素电极。

公开(公告)号：US20050221546A1

公开(公告)日：2005-10-06

申请号：US11082967

申请日：2005-03-18

Applicant: Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

Inventor： Woo-Geun Lee ,  Beom-Seok Cho ,  Je-Hun Lee ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Min-Seok Oh ,  Young-Wook Lee ,  Hee-Hwan Choe

IPC: G02F1/1368 ,  G09F9/30 ,  G09G3/36 ,  G09G3/38 ,  H01L21/00 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1288 ,  G02F2001/136236 ,  H01L21/31144 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733

Abstract: A method of manufacturing a thin film transistor array panel including forming a gate line on a substrate, forming a gate insulating layer on the gate line, forming a semiconductor layer on the gate insulating layer, forming a data line and a drain electrode on the semiconductor layer, depositing a passivation layer on the data line and the drain electrode, forming a photoresist including a first portion and a second portion, which is thinner than the first portion, on the passivation layer, etching the passivation layer using the photoresist as a mask to expose a portion of the drain electrode, removing the second portion of the photoresist, depositing a conductive film, and removing the first portion of the photoresist to form a pixel electrode on the exposed portion of the drain electrode.

Abstract translation: 一种制造薄膜晶体管阵列面板的方法，包括在衬底上形成栅极线，在栅极线上形成栅极绝缘层，在栅极绝缘层上形成半导体层，在半导体上形成数据线和漏电极 在所述数据线和所述漏电极上沉积钝化层，在所述钝化层上形成包含比所述第一部分薄的第一部分和第二部分的光致抗蚀剂，使用所述光致抗蚀剂作为掩模蚀刻所述钝化层 露出漏极的一部分，去除光致抗蚀剂的第二部分，沉积导电膜，以及去除光致抗蚀剂的第一部分，以在漏电极的暴露部分上形成像素电极。

公开(公告)号：US09147022B2

公开(公告)日：2015-09-29

申请号：US13481579

申请日：2012-05-25

Applicant: Je-Hun Lee ,  Byung-Du Ahn ,  Sei-Yong Park ,  Jun-Hyun Park ,  Jae-Woo Park ,  Dae-Hwan Kim ,  Sung-Chul Kim ,  Yong-Woo Jeon

Inventor： Je-Hun Lee ,  Byung-Du Ahn ,  Sei-Yong Park ,  Jun-Hyun Park ,  Jae-Woo Park ,  Dae-Hwan Kim ,  Sung-Chul Kim ,  Yong-Woo Jeon

IPC: G06F7/60 ,  G06F17/10 ,  G06F17/50

CPC classification number: G06F17/5036

Abstract: A method for calculating values of parameters of a TFT includes calculating a set of simulated current-voltage (I-V) values using state-density-functions over an entire energy band in a band gap of an amorphous semiconductor of the TFT. The method further includes comparing the set of simulated I-V values with a set of measured I-V values of the TFT to determine a value of a parameter of the TFT. The method may further include calculating values of an acceptor state-density-function gA using a set of electrostatic capacity-voltage (C-V) values of the TFT measured according to a frequency. The method may further include determining values of a donor state-density-function gD and values of an interface state-density-function Dit over the entire energy band in the band gap.

Abstract translation: 用于计算TFT的参数值的方法包括使用TFT的非晶半导体的带隙中的整个能带上的状态密度函数来计算一组模拟电流 - 电压（I-V）值。 所述方法还包括将所述一组模拟I-V值与所述TFT的测量I-V值的集合进行比较，以确定所述TFT的参数的值。 该方法还可以包括使用根据频率测量的TFT的一组静电电容电压（C-V）值来计算受主状态密度函数gA的值。 该方法还可以包括在带隙中的整个能带上确定施主状态密度函数gD的值和接口状态密度函数Dit的值。

公开(公告)号：US08841663B2

公开(公告)日：2014-09-23

申请号：US13080413

申请日：2011-04-05

Applicant: Je-Hun Lee ,  Jae-Woo Park ,  Byung-Du Ahn ,  Sei-Yong Park ,  Jun-Hyun Park

Inventor： Je-Hun Lee ,  Jae-Woo Park ,  Byung-Du Ahn ,  Sei-Yong Park ,  Jun-Hyun Park

IPC: H01L29/10 ,  H01L29/12 ,  H01L29/786 ,  H01L29/45

CPC classification number: H01L29/45 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696

Abstract: A thin-film transistor includes a gate electrode, a source electrode, a drain electrode, a gate insulation layer and an oxide semiconductor pattern. The source and drain electrodes include a first metal element with a first oxide formation free energy. The oxide semiconductor pattern has a first surface making contact with the gate insulation layer and a second surface making contact with the source and drain electrodes to be positioned at an opposite side of the first surface. The oxide semiconductor pattern includes an added element having a second oxide formation free energy having an absolute value greater than or equal to an absolute value of the first oxide formation free energy, wherein an amount of the added element included in a portion near the first surface is zero or smaller than an amount of the added element included in a portion near the second surface.

Abstract translation: 薄膜晶体管包括栅电极，源电极，漏电极，栅极绝缘层和氧化物半导体图案。 源极和漏极包括具有第一氧化物形成自由能的第一金属元件。 氧化物半导体图案具有与栅极绝缘层接触的第一表面和与源极和漏极电极接触以与第一表面相对的第二表面。 氧化物半导体图案包括具有绝对值大于或等于第一氧化物形成自由能的绝对值的第二氧化物形成自由能的添加元素，其中包括在第一表面附近的部分中的添加元素的量 为零或小于包含在靠近第二表面的部分中的添加元素的量。