公开(公告)号：US20060163736A1

公开(公告)日：2006-07-27

申请号：US11367790

申请日：2006-03-03

Applicant: Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

Inventor： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC: H01L23/52 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US07037835B2

公开(公告)日：2006-05-02

申请号：US10744277

申请日：2003-12-23

Applicant: Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

Inventor： Kyoung-woo Lee ,  Soo-geun Lee ,  Ki-chul Park ,  Won-sang Song

IPC: H01L21/44

CPC classification number: H01L21/76832 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are an interconnection of a semiconductor device which includes a capping layer and a method for forming the interconnection. The interconnection of the semiconductor device is a copper damascene interconnection where the capping layer is formed as a dual layer of a silicon nitride layer and silicon carbide layer on a copper layer processed by chemical mechanical polishing (CMP). Therefore, it is possible to maintain a high etching selectivity and a low dielectric constant of the silicon carbide layer while providing superior leakage suppression.

公开(公告)号：US06953745B2

公开(公告)日：2005-10-11

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。

公开(公告)号：US20050176243A1

公开(公告)日：2005-08-11

申请号：US11033208

申请日：2005-01-11

Applicant: Sang-cheol Han ,  Kyoung-woo Lee ,  Mi-young Kim

Inventor： Sang-cheol Han ,  Kyoung-woo Lee ,  Mi-young Kim

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76808 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829

Abstract: A method of forming a dual damascene semiconductor interconnection and an etchant composition specially adapted for stripping a sacrificial layer in a dual damascene fabrication process without profile damage to a dual damascene pattern are provided. The method includes sequentially forming a first etch stop layer, a first intermetal dielectric, a second intermetal dielectric, and a capping layer on a surface of a semiconductor substrate on which a lower metal wiring is formed; etching the first intermetal dielectric, the second intermetal dielectric, and the capping layer to form a via; forming a sacrificial layer within the via; etching the sacrificial layer, the second intermetal dielectric, and the capping layer to form a trench; removing the sacrificial layer remaining around the via using an etchant composition including NH4F, HF, H2O and a surfactant; and forming an upper metal wiring within the thus formed dual damascene pattern including the via and the trench. The preferred etchant composition for stripping a sacrificial layer in the foregoing dual damascene process consists essentially of NH4F, HF, H2O and a surfactant.

Abstract translation: 提供了形成双镶嵌半导体互连的方法和特别适于在双镶嵌制造工艺中剥离牺牲层而不对双镶嵌图案造成损伤的蚀刻剂组合物。 该方法包括在其上形成有下金属布线的半导体衬底的表面上顺序地形成第一蚀刻停止层，第一金属间电介质，第二金属间电介质和覆盖层; 蚀刻第一金属间电介质，第二金属间电介质和封盖层以形成通孔; 在通孔内形成牺牲层; 蚀刻牺牲层，第二金属间电介质和覆盖层以形成沟槽; 使用包括NH 4 F，HF，H 2 O和表面活性剂的蚀刻剂组合物除去残留在通孔周围的牺牲层; 以及在由此形成的包括通孔和沟槽的双镶嵌图案中形成上金属布线。 用于剥离前述双镶嵌方法中的牺牲层的优选蚀刻剂组合物基本上由NH 4 F，HF，H 2 O和表面活性剂组成。

公开(公告)号：US20050124149A1

公开(公告)日：2005-06-09

申请号：US10939930

申请日：2004-09-13

Applicant: Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

Inventor： Jae-Hak Kim ,  Young-Joon Moon ,  Kyoung-Woo Lee ,  Jeong-Wook Hwang

IPC: H01L21/28 ,  H01L21/311 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76808 ,  H01L21/31144

Abstract: There is provided a method of forming a dual damascene metal interconnection by employing a sacrificial metal oxide layer. The method includes preparing a semiconductor substrate. An interlayer insulating layer is formed on the semiconductor substrate, and a preliminary via hole is formed by patterning the interlayer insulating layer. A sacrificial via protecting layer is formed on the semiconductor substrate having the preliminary via hole to fill the preliminary via hole, and cover an upper surface of the interlayer insulating layer. A sacrificial metal oxide layer is formed on the sacrificial via protecting layer, the sacrificial metal oxide layer is patterned to form a sacrificial metal oxide pattern having an opening crossing over the preliminary via hole, and exposing the sacrificial via protecting layer. The sacrificial via protecting layer and the interlayer insulating layer are etched using the sacrificial metal oxide pattern as an etch mask to form a trench located inside the interlayer insulating layer.

Abstract translation: 提供了通过使用牺牲金属氧化物层形成双镶嵌金属互连的方法。 该方法包括制备半导体衬底。 在半导体基板上形成层间绝缘层，通过图案化层间绝缘层形成预备通孔。 在具有初步通孔的半导体衬底上形成牺牲通孔保护层以填充预通孔，并覆盖层间绝缘层的上表面。 在牺牲通路保护层上形成牺牲金属氧化物层，对牺牲金属氧化物层进行图案化以形成具有穿过预通孔的开口的牺牲金属氧化物图案，并且将牺牲通过保护层曝光。 使用牺牲金属氧化物图案作为蚀刻掩模蚀刻牺牲通过保护层和层间绝缘层，以形成位于层间绝缘层内部的沟槽。

公开(公告)号：US20050088551A1

公开(公告)日：2005-04-28

申请号：US10973291

申请日：2004-10-27

Applicant: Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

Inventor： Soo-Geun Lee ,  Ki-Chul Park ,  Kyoung-Woo Lee

IPC: G01R31/28 ,  H01L23/532 ,  H01L27/146 ,  H01L31/0224 ,  H04N17/00 ,  H04N5/335

CPC classification number: H01L23/53238 ,  G01R31/2829 ,  H01L21/76805 ,  H01L27/14603 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687 ,  H01L31/022408 ,  H01L2924/0002 ,  H04N17/002 ,  H01L2924/00

Abstract: An image sensor device and method for forming the same include a photodiode formed in a substrate, at least one electrical interconnection line electrically associated with the photodiode, a light passageway having a light inlet, the light passageway being positioned in alignment with the photodiode, a color filter positioned over the light inlet of the light passageway and a lens positioned over the color filter in alignment with the light passageway wherein the at least one electrical interconnection line includes a copper interconnection formation having a plurality of interlayer dielectric layers in a stacked configuration with a diffusion barrier layer between adjacent interlayer dielectric layers, and a barrier metal layer between the copper interconnection formation and the plurality of interlayer dielectric layers and intervening diffusion barrier layers. An image sensor device may employ copper interconnections if a barrier metal layer is removed from above a photodiode.

公开(公告)号：US06861347B2

公开(公告)日：2005-03-01

申请号：US10114274

申请日：2002-04-02

Applicant: Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

Inventor： Kyoung-woo Lee ,  Hong-jae Shin ,  Jae-hak Kim ,  Soo-geun Lee

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76808 ,  H01L21/76813 ,  H01L21/76835

Abstract: A method for forming a metal wiring layer in a semiconductor device using a dual damascene process is provided. A stopper layer, an interlayer insulating layer, and a hard mask layer are sequentially formed on a semiconductor substrate having a conductive layer. A first photoresist pattern that comprises a first opening having a first width is formed on the hard mask layer. The hard mask layer and portions of the interlayer insulating layer are etched using the first photoresist pattern as an etching mask, thereby forming a partial via hole having the first width. The first photoresist pattern is removed. An organic material layer is coated on the semiconductor substrate having the partial via hole is formed to fill the partial via hole with the organic material layer. A second photoresist pattern that comprises a second opening aligned with the partial via hole and having a second width greater than the first width is formed on the coated semiconductor substrate. The organic material layer and the hard mask layer on the interlayer insulating layer are etched using the second photoresist pattern as an etching mask. The second photoresist pattern and the organic material layer are simultaneously removed. A wiring region having the second width and a via hole having the first width are formed by etching the interlayer insulating layer using the hard mask layer as an etching mask.

Abstract translation: 提供了一种使用双镶嵌工艺在半导体器件中形成金属布线层的方法。 在具有导电层的半导体衬底上依次形成阻挡层，层间绝缘层和硬掩模层。 包括具有第一宽度的第一开口的第一光致抗蚀剂图案形成在硬掩模层上。 使用第一光致抗蚀剂图案作为蚀刻掩模来蚀刻硬掩模层和层间绝缘层的部分，从而形成具有第一宽度的部分通孔。 去除第一光致抗蚀剂图案。 在半导体基板上涂布有机材料层，其中形成有部分通孔以用有机材料层填充部分通孔。 在涂覆的半导体衬底上形成第二光致抗蚀剂图案，该第二光致抗蚀剂图案包括与部分通路孔对准的第二开口，并具有大于第一宽度的第二宽度。 使用第二光致抗蚀剂图案作为蚀刻掩模蚀刻层间绝缘层上的有机材料层和硬掩模层。 同时去除第二光致抗蚀剂图案和有机材料层。 通过使用硬掩模层作为蚀刻掩模蚀刻层间绝缘层，形成具有第二宽度的布线区域和具有第一宽度的通孔。

公开(公告)号：US6158017A

公开(公告)日：2000-12-05

申请号：US39679

申请日：1998-03-16

Applicant: Tack-Don Han ,  Shin-Dug Kim ,  Sung-Bong Yang ,  Kyoung-Woo Lee ,  Suk Chang

Inventor： Tack-Don Han ,  Shin-Dug Kim ,  Sung-Bong Yang ,  Kyoung-Woo Lee ,  Suk Chang

IPC: G06F12/16 ,  G06F3/06 ,  G06F11/10 ,  H03M13/00 ,  H03M13/09 ,  H03M13/29

CPC classification number: G06F11/1076 ,  H03M13/00 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2921 ,  H03M13/6561

Abstract: A method for storing parity and rebuilding the data contents of two failed disks in an external storage subsystem comprises the steps of: proving a disk array defined as a matrix of (N-1).sup.* N including N disks each logically divided into N-1 data blocks where N is a prime number, the data blocks of a row being defined as a horizontal parity group, the data blocks existing in a rightwardly and upwardly continuous diagonal line being defined as a diagonal parity group; defining the data blocks existing in the diagonal line leftwardly and downwardly from the first data block of the (N-1) disk to the last data block of the first disk as horizontal parity blocks; defining the data blocks existing in the (N-1) row of the matrix as diagonal parity blocks; exclusive OR'ing (XORing) the contents of each of the horizontal and diagonal parity groups to obtain the parity value stored into the parity block of the corresponding horizontal or diagonal parity group; and analyzing a diagonal parity group including an error data block of the two failed disks to restore the error data block and then, the horizontal parity group including the restored error data block to restore another error data block, wherein the last analyzing step is repeated to completely rebuild the data contents of the two failed disks.

Abstract translation: 一种在外部存储子系统中存储奇偶校验和重建两个故障磁盘的数据内容的方法，包括以下步骤：证明定义为包括N个磁盘的（N-1）* N的矩阵的磁盘阵列，每个N个磁盘每个逻辑上划分为N-1个 数据块，其中N是素数，一行的数据块被定义为水平奇偶校验组，存在于向右和向上连续的对角线中的数据块被定义为对角奇偶校验组; 将存在于对角线中的数据块从（N-1）盘的第一数据块向左和向下定位为第一盘的最后数据块作为水平校验块; 将存在于矩阵的（N-1）行中的数据块定义为对角奇偶校验块; 对每个水平和对角奇偶校验组的内容进行异或运算（异或），以获得存储在相应的水平或对角奇偶校验组的奇偶校验块中的奇偶校验值; 并且分析包括两个故障磁盘的错误数据块的对角奇偶校验组以恢复错误数据块，然后，包括恢复的错误数据块的水平奇偶校验组以恢复另一个错误数据块，其中重复最后一个分析步骤 完全重建两个故障磁盘的数据内容。