公开(公告)号：US20080174924A1

公开(公告)日：2008-07-24

申请号：US11969966

申请日：2008-01-07

申请人： Myoung-Gon KANG ,  Ki-Whan SONG

发明人： Myoung-Gon KANG ,  Ki-Whan SONG

IPC分类号： H02H9/00

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electrostatic discharge (ESD) protection device includes an I/O terminal structure and a current discharge structure. The current discharge structure includes a conductive region separated from a bridge region by a gate electrode, a well region formed below the conductive region, another well region separated from the well region by another conductive region, and multiple additional conductive regions implementing dual current discharge paths through another well region.

摘要翻译： 静电放电（ESD）保护装置包括I / O端子结构和电流放电结构。 电流放电结构包括通过栅极电极与桥接区域分离的导电区域，形成在导电区域下方的阱区域，通过另一导电区域与阱区域分离的另一阱区域以及实现双电流放电路径的多个附加导电区域 通过另一个井区。

公开(公告)号：US20080142868A1

公开(公告)日：2008-06-19

申请号：US11853044

申请日：2007-09-11

申请人： Nam-Kyun TAK ,  Ki-Whan SONG

发明人： Nam-Kyun TAK ,  Ki-Whan SONG

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A floating body memory includes a semiconductor substrate having a cell region and a peripheral circuit region. A floating body cell is located in the cell region and a first floating body is located in the peripheral circuit region of the semiconductor substrate. A peripheral gate pattern is positioned on the first floating body. First source and drain regions are positioned at both sides of the peripheral gate pattern. First leakage shielding patterns are positioned between the first floating body and the first source and drain regions, the first source and drain regions contacting the first floating body. The first leakage shielding patterns may be positioned outside outer edges of the peripheral gate pattern.

摘要翻译： 浮体存储器包括具有单元区域和外围电路区域的半导体衬底。 浮体单元位于单元区域中，第一浮体位于半导体基板的外围电路区域中。 外围门图案位于第一浮体上。 第一源极和漏极区域位于外围栅极图案的两侧。 第一泄漏屏蔽图案位于第一浮体和第一源漏区之间，第一源区和漏区接触第一浮体。 第一泄漏屏蔽图案可以位于外围栅极图案的外边缘外侧。

公开(公告)号：US20070166933A1

公开(公告)日：2007-07-19

申请号：US11622584

申请日：2007-01-12

申请人： Ki-whan Song ,  Chang-kyun Kim

发明人： Ki-whan Song ,  Chang-kyun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L29/66772 ,  H01L29/7841

摘要： Methods of forming capacitor-free DRAM cells include forming a field effect transistor by forming a first semiconductor wafer having a channel region protrusion extending therefrom and surrounding the channel region protrusion by an electrical isolation region. A portion of a backside of the first semiconductor wafer is then removed to define a semiconductor layer having a primary surface extending opposite the channel region protrusion and the electrical isolation region. A gate electrode is formed on the primary surface. The gate electrode extends opposite the channel region protrusion. The source and drain regions are formed in the semiconductor layer, on opposite sides of the gate electrode.

摘要翻译： 形成无电容器的DRAM单元的方法包括通过形成具有从其延伸的沟道区突起并且通过电隔离区围绕沟道区突起的第一半导体晶片来形成场效应晶体管。 然后去除第一半导体晶片的背面的一部分以限定具有与沟道区域突起和电隔离区域相对延伸的主表面的半导体层。 在主表面上形成栅电极。 栅电极与沟道区突起相对延伸。 源极和漏极区域形成在栅电极的相对侧上的半导体层中。

公开(公告)号：US20070159903A1

公开(公告)日：2007-07-12

申请号：US11546421

申请日：2006-10-12

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

IPC分类号： G11C7/02

CPC分类号： G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

摘要： In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

摘要翻译： 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

公开(公告)号：US20070139994A1

公开(公告)日：2007-06-21

申请号：US11637519

申请日：2006-12-12

申请人： Ki-whan Song ,  Yeong-taek Lee

发明人： Ki-whan Song ,  Yeong-taek Lee

IPC分类号： G11C11/24

CPC分类号： G11C11/24

摘要： A multi-level dynamic memory device having an open bit line structure is disclosed. The multi-level dynamic memory device includes a plurality of word lines; a plurality of bit lines provided in an open bit line structure; a plurality of memory cells each of which is connected to each of the word lines and each of the bit lines and stores at least two bits of data; and a plurality of sense amplifiers, each of which amplifies a voltage difference between the bit lines, the bit lines being located at opposite sides of each of the plurality of sense amplifiers.

摘要翻译： 公开了一种具有开放位线结构的多级动态存储器件。 多级动态存储装置包括多个字线; 设置在开放位线结构中的多个位线; 多个存储单元，每个存储单元连接到每个字线和每个位线，并存储至少两位数据; 以及多个读出放大器，每个读出放大器放大位线之间的电压差，位线位于多个读出放大器的每一个的相对侧。

公开(公告)号：US06707653B2

公开(公告)日：2004-03-16

申请号：US10251979

申请日：2002-09-23

申请人： Dong-Jin Lee ,  Ki-Whan Song

发明人： Dong-Jin Lee ,  Ki-Whan Song

IPC分类号： H02H900

CPC分类号： H01L27/0262

摘要： An electrostatic discharge (ESD) protection circuit includes an MOS transistor acting as a trigger for the circuit. A drain region of the MOS transistor is formed by an N-type heavily doped impurity region which overlaps an N-type well region. Further, a P-type heavily doped impurity region is formed in the N-type well region. The N-type and P-type heavily doped impurity regions are electrically connected to an input/output pad. The ESD protection circuit exhibits a reduced input capacitance at the pad, and a reduced breakdown voltage of the MOS transistor.

摘要翻译： 静电放电（ESD）保护电路包括用作电路触发器的MOS晶体管。 MOS晶体管的漏极区域与N型阱区域重叠的N型重掺杂杂质区域形成。 此外，在N型阱区中形成P型重掺杂杂质区。 N型和P型重掺杂杂质区域电连接到输入/输出焊盘。 ESD保护电路在焊盘处表现出降低的输入电容，并且降低了MOS晶体管的击穿电压。

公开(公告)号：US06366113B1

公开(公告)日：2002-04-02

申请号：US09716557

申请日：2000-11-20

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： H03K30233

CPC分类号： H03K3/013 ,  H03K3/012 ,  H03K3/356139

摘要： A data receiver is provided for stabilizing a reference voltage to which input data is compared. The data receiver includes a differential amplification flip flop for comparing input data to a reference voltage in response to a clock signal, an amplifier for amplifying the results of the comparison, a latch for storing the logic level of the input data, and a counter coupling circuit for reducing the variation of the reference voltage caused by the operation of the differential amplification flip flop in response to an inverted clock signal. In the data receiver, the reference voltage is stably preserved without minimized variation. Also, there is substantially no consumption of direct current (DC) when the data receiver operates.

摘要翻译： 提供数据接收器用于稳定比较输入数据的参考电压。 数据接收机包括差分放大触发器，用于响应于时钟信号将输入数据与参考电压进行比较，用于放大比较结果的放大器，用于存储输入数据的逻辑电平的锁存器和反耦合器 电路，用于响应于反相时钟信号减小由差分放大触发器的操作引起的参考电压的变化。 在数据接收机中，参考电压被稳定地保持而没有最小化的变化。 此外，当数据接收器工作时，基本上不消耗直流电（DC）。

公开(公告)号：US09342447B2

公开(公告)日：2016-05-17

申请号：US13957901

申请日：2013-08-02

申请人： Kyung-Ryun Kim ,  Sang-Yong Yoon ,  Ki-Whan Song

发明人： Kyung-Ryun Kim ,  Sang-Yong Yoon ,  Ki-Whan Song

IPC分类号： G11C16/00 ,  G06F12/02 ,  G11C11/56 ,  G11C16/34

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： A method of operating a data storage device includes providing a memory cell array that includes a first word line, a second word line and a buffer configured to store second data to be programmed into the second word line, reading the second data from the buffer, and programming first data into the first word line. A programming condition of the first data being is changed based on the second data read from the buffer.

摘要翻译： 一种操作数据存储装置的方法包括：提供包括第一字线，第二字线和被配置为将待编程的第二数据存储到第二字线中的缓冲器的存储单元阵列，从缓冲器读取第二数据， 并将第一个数据编程到第一个字线。 基于从缓冲器读取的第二数据，改变第一数据的编程条件。

公开(公告)号：US08724411B2

公开(公告)日：2014-05-13

申请号：US13251611

申请日：2011-10-03

申请人： Jin-Young Kim ,  Ki Whan Song ,  Jae Hee Oh ,  Ji-Hyun Jeong

发明人： Jin-Young Kim ,  Ki Whan Song ,  Jae Hee Oh ,  Ji-Hyun Jeong

IPC分类号： G11C7/00

CPC分类号： H01L27/2409 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2436

摘要： A non-volatile memory device can include a word line that is operatively coupled to a non-volatile memory cell. A local bit line can be operatively coupled to the non-volatile memory cell. A discharge line that is associated with the local bit line can be configured to discharge the local bit line and a discharge diode can be electrically coupled between the local bit line and the discharge line.

摘要翻译： 非易失性存储器件可以包括可操作地耦合到非易失性存储器单元的字线。 局部位线可以可操作地耦合到非易失性存储单元。 与本地位线相关联的放电线可以被配置为放电本地位线，并且放电二极管可以电耦合在局部位线和放电线之间。

公开(公告)号：US20140047168A1

公开(公告)日：2014-02-13

申请号：US13957901

申请日：2013-08-02

申请人： KYUNG-RYUN KIM ,  KYUNG-RYUN KIM ,  KI-WHAN SONG

发明人： KYUNG-RYUN KIM ,  KYUNG-RYUN KIM ,  KI-WHAN SONG

IPC分类号： G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7203 ,  G11C11/5628 ,  G11C16/3418 ,  G11C16/3427

摘要： A method of operating a data storage device includes providing a memory cell array that includes a first word line, a second word line and a buffer configured to store second data to be programmed into the second word line, reading the second data from the buffer, and programming first data into the first word line. A programming condition of the first data being is changed based on the second data read from the buffer.

摘要翻译： 一种操作数据存储装置的方法包括：提供包括第一字线，第二字线和被配置为将待编程的第二数据存储到第二字线中的缓冲器的存储单元阵列，从缓冲器读取第二数据， 并将第一个数据编程到第一个字线。 基于从缓冲器读取的第二数据，改变第一数据的编程条件。