公开(公告)号：US11069715B2

公开(公告)日：2021-07-20

申请号：US16285245

申请日：2019-02-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shyng-Yeuan Che ,  Shih-Ping Lee

IPC分类号： H01L27/12 ,  H01L29/06 ,  H01L21/308 ,  H01L49/02 ,  H01L21/768 ,  H01L29/78

摘要： A memory structure including a SOI substrate, a first transistor, a second transistor, an isolation structure and a capacitor is provided. The SOI substrate includes a silicon base, a dielectric layer and a silicon layer. The first transistor and the second transistor are disposed on the silicon layer. The isolation structure is disposed in the silicon layer between the first transistor and the second transistor. The capacitor is disposed between the first transistor and the second transistor. The capacitor includes a body portion, a first extension portion, a second extension portion and a third extension portion. The first extension portion extends from the body portion to a source/drain region of the first transistor. The second extension portion extends from the body portion to a source/drain region of the second transistor. The third extension portion extends from the body portion, penetrates through the isolation structure and extends into the dielectric layer.

公开(公告)号：US11063141B1

公开(公告)日：2021-07-13

申请号：US16883997

申请日：2020-05-26

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chun-Sheng Chen

IPC分类号： H01L29/739 ,  H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/417 ,  H01L29/66

摘要： An insulated gate field effect bipolar transistor (IGFEBT) includes a substrate, a deep well (DW) region, a first conductivity type well region, a gate structure, a source region and a drain region located on the first conductivity type well region at both sides of the gate structure, an anode, and a cathode. The source region includes a first doped region and a second doped region between the first doped region and the gate structure, and the drain region includes a third doped region and a fourth doped region formed on the third doped region. The substrate, the first and fourth doped regions are of the first conductivity type, and the DW region, the second and the third doped regions are of a second conductivity type. The anode is electrically coupled to the fourth doped region, and the cathode is electrically coupled to the first and second doped regions.

公开(公告)号：US20210091067A1

公开(公告)日：2021-03-25

申请号：US17115799

申请日：2020-12-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wei-Yu Lin ,  Shih-Hao Cheng

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

摘要： A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.

公开(公告)号：US10910368B1

公开(公告)日：2021-02-02

申请号：US16575407

申请日：2019-09-19

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chun-Sheng Chen

IPC分类号： H01L27/085 ,  H01L29/06 ,  H01L29/423 ,  G11C11/412 ,  H01L29/10 ,  H03K3/353 ,  H03K19/20 ,  H01L29/66

摘要： A circuit structure including a first gate structure, a first multi-connected channel layer and a second transistor is provided. The first gate structure has a first extension direction, and the first gate structure has a first end and a second end opposite to each other. The first gate structure is fully surrounded by the first multi-connected channel layer, and a plane direction of the multi-connected channel layer is perpendicular to the first extension direction. The first gate structure and the first multi-connected channel layer form a first transistor. The second transistor is disposed in the first multi-connected channel layer. A second gate structure or a channel of the second transistor is electrical connected to the first multi-connected channel layer.

公开(公告)号：US10903203B2

公开(公告)日：2021-01-26

申请号：US16168839

申请日：2018-10-24

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wei-Yu Lin ,  Shih-Hao Cheng

IPC分类号： H01L27/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/739

摘要： A trench transistor structure includes a substrate structure, a transistor device, and an electrostatic discharge (ESD) protection device. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. The transistor device is located in the first region and includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. The ESD protection device is located in the second region and includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.

公开(公告)号：US20210020778A1

公开(公告)日：2021-01-21

申请号：US16663365

申请日：2019-10-25

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-I Su ,  Chang-Chin Ho ,  Yong-Kang Jiang

IPC分类号： H01L29/78 ,  H01L29/40 ,  H01L29/66

摘要： A shield gate MOSFET includes an epitaxial layer having a first conductivity type, a plurality of trenches in the epitaxial layer, a shield gate disposed in the trenches, a control gate on the shield gate in the trenches, an insulating layer between the shield gate and the epitaxial layer, a gate oxide layer between the control gate and the epitaxial layer, an inter-gate oxide layer between the shield gate and the control gate, a first doped region in the epitaxial layer at the bottom of the trenches, and a second doped region between the bottom of the trenches and the first doped region. The first doped region has a second conductivity type, and the second doped region has the first conductivity type, and thus the leakage path may be reduced in the presence of the second doped region so as to improve breakdown voltage.

公开(公告)号：US10825508B1

公开(公告)日：2020-11-03

申请号：US16712878

申请日：2019-12-12

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Pei-Hsiu Tseng ,  I-Shuan Wei ,  Jia-You Lin ,  Shou-Zen Chang ,  Chi-Wei Lin ,  Hung-Hsun Lin

IPC分类号： G11C11/4097 ,  H01L27/11 ,  G11C11/404 ,  H01L27/108

摘要： A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.

公开(公告)号：US10803961B2

公开(公告)日：2020-10-13

申请号：US16294948

申请日：2019-03-07

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Tomofumi Kitani

IPC分类号： G11C16/30 ,  G11C16/32 ,  G06F1/26 ,  G11C16/04

摘要： A comparator (13) compares a pad voltage with a reference voltage (Vref1) to output a voltage (VCCOK), and a comparator (23) compares a low voltage with a reference voltage (Vref2) to output a voltage (VDDOK). A power-on circuit (2) includes a timer circuit (11) and starts a reference voltage generation circuit (12) after the power switch control circuit is started, and then starts the comparator (13). After the comparator (13) is started, a controller (30) starts a voltage down converter (4) when the voltage (VCCOK) is at the H level, and turns on a MOS transistor (Q1) when the voltage (VCCOK) is at the L level. A power-on circuit (3) includes a timer circuit (21) and starts a reference voltage generation circuit (22) after the voltage down converter (4) is started, and then starts a comparator (23). After the comparator (23) is started, the controller (30) enters the standby state.

公开(公告)号：US10784259B2

公开(公告)日：2020-09-22

申请号：US16357343

申请日：2019-03-19

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Hung-Kwei Liao ,  Chen-Chiang Liu ,  Kuo-Sheng Shih ,  Yung-Yao Shih ,  Ming-Tsung Hsu

IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L21/28 ,  H01L21/311 ,  H01L21/321 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/49 ,  H01L21/3215 ,  H01L21/027

摘要： Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.

公开(公告)号：US20200286565A1

公开(公告)日：2020-09-10

申请号：US16574099

申请日：2019-09-18

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： MATHIAS YVES GILBERT BAYLE

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/32 ,  G11C16/34

摘要： The disclosure controls the erase voltage with higher accuracy than the related art when erasing data in a non-volatile semiconductor memory device. An control circuit for controlling an erase voltage includes: a slope adjustment circuit that controls a slope having a step shape by controlling a step voltage, a target voltage, and a step width of the erase voltage. The slope adjustment circuit repeatedly increases the erase voltage by the step voltage for each predetermined clock pulse control signal to the target voltage based on the step voltage and the target voltage, and outputs the clock pulse control signal to the erase voltage generation circuit by repeatedly clocking each time interval corresponding to the step width based on the step width.