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201 records (took 0.038 seconds)

    Power on reset (POR) circuit
    91.
    发明授权
    Power on reset (POR) circuit 有权

    公开(公告)号：US09760108B2

    公开(公告)日：2017-09-12

    申请号：US14887739

    申请日：2015-10-20

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Yong Feng Liu

    IPC: G05F3/26

    CPC classification number: G05F3/267

    Abstract: A Schmitt trigger circuit having an input coupled to a current summing junction. A trickle current source generates a trickle current applied to the current summing junction. A bandgap current source generates a bandgap current applied to the current summing junction (wherein the bandgap current is fixed when a supply voltage exceeds a threshold). A variable current source generates a variable current applied to the current summing junction (wherein the variable current varies dependent on the supply voltage). At the current summing junction, the variable current is offset against the trickle and bandgap currents with respect to generating a voltage that is sensed at the Schmitt trigger circuit input.

    Dynamic threshold generator for use in adaptive body biasing of a MOS
    96.
    发明授权
    Dynamic threshold generator for use in adaptive body biasing of a MOS 有权

    公开(公告)号：US09667138B2

    公开(公告)日：2017-05-30

    申请号：US14825267

    申请日：2015-08-13

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Min Chen ,  Wen Liu

    IPC: H02M3/08 ,  G05F3/20 ,  G05F3/24

    CPC classification number: H02M3/08 ,  G05F3/205 ,  G05F3/242 ,  H03K17/302 ,  H03K2217/0018

    Abstract: An electronic device includes a transistor having a body and a body biasing circuit. The body biasing circuit includes a threshold estimator circuit to estimate a threshold voltage of the transistor and a comparison circuit to compare the threshold voltage of the transistor to a reference threshold voltage and to generate a comparison signal based thereupon. A bias adjust circuit generates a body biasing voltage that biases the body of the transistor as a function of the comparison signal, the body biasing voltage being a voltage that, when applied to the body of the transistor, adjusts the threshold voltage thereof to be equal to the reference threshold voltage.

    Driver circuit with gate clamp supporting stress testing
    97.
    发明授权
    Driver circuit with gate clamp supporting stress testing 有权
    驱动电路与门夹支持压力测试

    公开(公告)号：US09490786B2

    公开(公告)日：2016-11-08

    申请号：US15088898

    申请日：2016-04-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: H03B1/00 ,  H03K3/00 ,  H03K5/08 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

    Image sensor device with aligned IR filter and dielectric layer and related methods
    98.
    发明授权
    Image sensor device with aligned IR filter and dielectric layer and related methods 有权
    具有对准IR滤光片和介电层的图像传感器器件及相关方法

    公开(公告)号：US09419047B2

    公开(公告)日：2016-08-16

    申请号：US14135743

    申请日：2013-12-20

    Applicant: STMICROELECTRONICS (SHENZHEN) R&D CO., LTD.

    Inventor： Jing-En Luan

    IPC: H04N5/33 ,  H01L27/146 ,  H04N5/225

    CPC classification number: H01L27/14683 ,  H01L27/14618 ,  H01L2224/13 ,  H01L2224/73265 ,  H04N5/2254 ,  H04N5/2257

    Abstract: An image sensor device may include an interconnect layer, an image sensor IC adjacent the interconnect layer and having an image sensing surface, and a dielectric layer adjacent the image sensor IC and having an opening therein aligned with the image sensing surface. The image sensor device may also include an IR filter adjacent and aligned with the image sensing surface, and an encapsulation material adjacent the dielectric layer and laterally surrounding the IR filter.

    Abstract translation: 图像传感器装置可以包括互连层，邻近互连层并具有图像感测表面的图像传感器IC，以及邻近图像传感器IC的电介质层，并且具有与图像感测表面对准的开口。 图像传感器装置还可以包括与图像感测表面相邻并对齐的IR滤光器，以及邻近介电层并横向围绕IR滤光器的封装材料。

    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING
    99.
    发明申请
    DRIVER CIRCUIT WITH GATE CLAMP SUPPORTING STRESS TESTING 审中-公开
    带门夹的驱动电路支持应力测试

    公开(公告)号：US20160218700A1

    公开(公告)日：2016-07-28

    申请号：US15088898

    申请日：2016-04-01

    Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

    Inventor： Ni Zeng

    IPC: H03K5/08 ,  H03K17/687

    CPC classification number: H03K5/08 ,  G01R31/2621 ,  H03K3/011 ,  H03K17/08122 ,  H03K17/687

    Abstract: A generator circuit is coupled to apply a control signal to the gate terminal of a power transistor driving an output node. A reference voltage is generated having a first voltage value as the reference for the control signal and having a second, higher, voltage value for use in stress testing. A clamping circuit is provided between the reference voltage and the power transistor gate to function in two modes. In one mode, the clamping circuit applies a first clamp voltage to clamp the voltage at the gate of the power transistor when the generator circuit is applying the control signal. In another mode, the clamping circuit applies a second, higher, clamp voltage to clamp the gate of the power transistor during gate stress testing.

    Abstract translation: 发电机电路被耦合以将控制信号施加到驱动输出节点的功率晶体管的栅极端子。 产生参考电压，其具有第一电压值作为控制信号的基准，并具有用于应力测试的第二，较高的电压值。 在参考电压和功率晶体管栅极之间提供钳位电路，以在两种模式下起作用。 在一种模式中，当发电机电路施加控制信号时，钳位电路施加第一钳位电压以钳位功率晶体管的栅极处的电压。 在另一种模式下，钳位电路在栅极压力测试期间施加第二个较高的钳位电压来钳位功率晶体管的栅极。

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