公开(公告)号：US20090250756A1

公开(公告)日：2009-10-08

申请号：US12485777

申请日：2009-06-16

Applicant: Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

Inventor： Yark Yeon Kim ,  Moon Gyu Jang ,  Jae Heon Shin ,  Seong Jae Lee

IPC: H01L27/12

CPC classification number: H01L29/665 ,  H01L21/2252 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/28537 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7839

Abstract: An n-type SBTT and a manufacturing method thereof are provided. The SBTT includes a silicon layer, a gate, a double layer that has a rare-earth metal silicide layer and a transition metal silicide layer. The silicon layer has a channel region. The gate is formed in an overlapping manner on the channel region and has a gate dielectric layer on its interface with respect to the silicon layer. The double layer is formed as a source/drain that has the channel region interposed on the silicon layer.

Abstract translation: 提供了n型SBTT及其制造方法。 SBTT包括硅层，栅极，具有稀土金属硅化物层和过渡金属硅化物层的双层。 硅层具有沟道区。 栅极以重叠的方式形成在沟道区上，并且在其相对于硅层的界面上具有栅极介电层。 双层形成为具有介于硅层之间的沟道区的源极/漏极。

公开(公告)号：US20080128786A1

公开(公告)日：2008-06-05

申请号：US11950291

申请日：2007-12-04

Applicant: Taeyoub KIM ,  Myungsim JUN ,  Yark-Yeon KIM ,  Moon-Gyu JANG ,  Chel-Jong CHOI ,  Seong-Jae LEE ,  Byoungchul PARK

Inventor： Taeyoub KIM ,  Myungsim JUN ,  Yark-Yeon KIM ,  Moon-Gyu JANG ,  Chel-Jong CHOI ,  Seong-Jae LEE ,  Byoungchul PARK

IPC: H01L29/788 ,  H01L21/336

CPC classification number: H01L29/788 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/41725 ,  H01L29/42324 ,  H01L29/47 ,  H01L29/66825 ,  H01L29/7839 ,  H01L29/78654 ,  H01L29/7881

Abstract: Provided are a high density semiconductor memory device capable of precisely reading data by suppressing the occurrence of a leakage current due to the high-integration of the semiconductor memory device, and a method for manufacturing the semiconductor memory device. The high density semiconductor memory device includes: source and drain electrodes disposed over a substrate, and forming a Schottky junction with a channel region; and a floating gate disposed over the substrate of the channel region, and configured with a plurality of nanodots. The nanodots may be formed of a silicon compound or any material that can be charged.

Abstract translation: 提供一种能够通过抑制由于半导体存储器件的高集成度而导致的漏电流的发生而精确读取数据的高密度半导体存储器件以及半导体存储器件的制造方法。 高密度半导体存储器件包括：源极和漏极，设置在衬底上，并与沟道区形成肖特基结; 以及浮置栅极，设置在沟道区域的衬底上，并且配置有多个纳米点。 纳米点可以由硅化合物或可以被充电的任何材料形成。

公开(公告)号：US07312510B2

公开(公告)日：2007-12-25

申请号：US11187654

申请日：2005-07-22

Applicant: Jae Heon Shin ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Seong Jae Lee

Inventor： Jae Heon Shin ,  Moon Gyu Jang ,  Yark Yeon Kim ,  Seong Jae Lee

IPC: H01L29/47

CPC classification number: H01L29/7839 ,  G11C11/56

Abstract: A device using an ambipolar transport of an SB-MOSFET and a method for operating the same are provided. The SB-MOSFET includes: a silicon channel region; a source and a drain contacted on both sides of the channel region and formed of material including metal layer; and a gate formed on the channel region, with a gate dielectric layer interposed therebetween. Positive (+), 0 or negative (−) gate voltage is selectively applied to the gate, the channel becomes off-state when the gate voltage between a negative threshold voltage and a positive threshold voltage is applied, and the channel becomes a first on-state and a second on-state when the gate voltage is lower than the negative threshold voltage or higher than the positive threshold voltage. Accordingly, it is possible to implement three current states, that is, hole current, electron current, and no current. The SB-MOSFET can be applied to a multi-bit memory and/or multi-bit logic device.

Abstract translation: 提供了使用SB-MOSFET的双极运输的装置及其操作方法。 SB-MOSFET包括：硅沟道区; 源极和漏极在沟道区域的两侧接触并由包括金属层的材料形成; 以及形成在沟道区上的栅极，介于其间的栅介质层。 正极（+），0或负（ - ）栅极电压选择性地施加到栅极，当施加负阈值电压和正阈值电压之间的栅极电压时，通道变为截止状态，并且通道变为第一个 当门电压低于负阈值电压或高于正阈值电压时，状态和第二导通状态。 因此，可以实现三种电流状态，即空穴电流，电子电流，无电流。 SB-MOSFET可以应用于多位存储器和/或多位逻辑器件。

公开(公告)号：US07268407B2

公开(公告)日：2007-09-11

申请号：US11196180

申请日：2005-08-03

Applicant: Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

Inventor： Moon Gyu Jang ,  Yark Yeon Kim ,  Jae Heon Shin ,  Seong Jae Lee

IPC: H01L31/07

CPC classification number: H01L29/7613 ,  B82Y10/00 ,  H01L29/872

Abstract: Provided are a Schottky barrier tunnel single electron transistor and a method of manufacturing the same that use a Schottky barrier formed between metal and semiconductor by replacing a source and a drain with silicide as a reactant of silicon and metal, instead of a conventional method of manufacturing a single electron transistor (SET) that includes source and drain regions by implanting dopants such that an artificial quantum dot is formed in a channel region. As a result, it does not require a conventional PADOX process to form a quantum dot for a single electron transistor (SET), height and width of a tunneling barrier can be artificially adjusted by using silicide materials that have various Schottky junction barriers, and it is possible to improve current driving capability of the single electron transistor (SET).

Abstract translation: 提供了一种肖特基势垒隧道单电子晶体管及其制造方法，其替代传统的制造方法，而是用硅化物替代源极和漏极作为硅和金属的反应物，从而形成金属和半导体之间形成的肖特基势垒 单电子晶体管（SET），其通过注入掺杂剂而包括源极和漏极区域，使得在沟道区域中形成人造量子点。 结果，不需要传统的PADOX工艺来形成单电子晶体管（SET）的量子点，隧道势垒的高度和宽度可以通过使用具有各种肖特基结屏障的硅化物材料进行人工调整，而且 可以提高单电子晶体管（SET）的电流驱动能力。

公开(公告)号：US20070057668A1

公开(公告)日：2007-03-15

申请号：US11459157

申请日：2006-07-21

Applicant: Seong-Jae Lee ,  Sang-Hoon Song ,  Yevgen Melikhov ,  Choon-Mahn Park ,  Hans Hauser ,  David Jiles

Inventor： Seong-Jae Lee ,  Sang-Hoon Song ,  Yevgen Melikhov ,  Choon-Mahn Park ,  Hans Hauser ,  David Jiles

IPC: G01N27/82

CPC classification number: G01N21/21 ,  G01D5/145 ,  G01N21/1717

Abstract: A system and method to detect angular rotation, linear displacement and/or surface deformations is presented. The method is based on the ability of a linear polarized light to interact with magnetic materials and to change its polarization angle due to Faraday effect. A basic structure of the system consists of a magneto-optic (MO) film with a two-domain structure and a single domain wall which are generated by gradient magnetic field produced by opposite polarity permanent magnets placed near the film. An AC magnetic field applied perpendicular to the MO film surface causes the magnetic domain wall in the MO film to oscillate at the same frequency. This leads to a detected output AC modulated signal. By measuring the temporal changes in this signal, information on angular rotation, linear displacement and/or surface deformation can be obtained.

Abstract translation: 提出了检测角旋转，线性位移和/或表面变形的系统和方法。 该方法基于线性偏振光与磁性材料相互作用并由于法拉第效应而改变其偏振角的能力。 系统的基本结构由具有双畴结构的磁光（MO）膜和由放置在膜附近的相反极性永磁体产生的梯度磁场产生的单畴壁组成。 垂直于MO膜表面施加的AC磁场使得MO膜中的磁畴壁以相同的频率振荡。 这导致检测到的输出AC调制信号。 通过测量该信号的时间变化，可以获得关于角旋转，线性位移和/或表面变形的信息。

公开(公告)号：US07187933B2

公开(公告)日：2007-03-06

申请号：US11331221

申请日：2006-01-13

Applicant: Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

Inventor： Bong Yong Song ,  Jeong Chul Kim ,  Youl No Lee ,  Gab Seok Jang ,  Se Hyun Oh ,  Seong Jae Lee

IPC: H04Q7/20 ,  H04Q7/00 ,  H04B7/216

CPC classification number: H04W72/0466 ,  H04B17/318 ,  H04B17/382 ,  H04B2201/70702 ,  H04W16/14 ,  H04W28/26 ,  H04W52/0206 ,  H04W72/02 ,  H04W72/0453 ,  H04W72/082 ,  H04W76/10 ,  H04W84/042 ,  Y02D70/00

Abstract: A method for assigning a channel in multi-FA CDMA mobile communication system according to the received power prevents communication quality of a FA from being inferior to that of the others by managing the interference level of the FA. The method comprises the steps of: comparing a first threshold value with received power when the base station receives a new call request; assigning a traffic channel in a first FA of the request, if the received power is less than the first threshold value, and searching a second FA of which received power is least, if not; comparing a second threshold value with the received power of the second FA; and assigning a traffic channel in the second FA if the received power is less than the second threshold value, and rejecting the request, if not.

Abstract translation: 根据接收到的功率，在多FA CDMA移动通信系统中分配信道的方法通过管理FA的干扰电平来防止FA的通信质量劣于其他信道。 该方法包括以下步骤：当基站接收到新的呼叫请求时，将第一阈值与接收功率进行比较; 如果接收功率小于第一阈值，则将业务信道分配到请求的第一FA中，并且如果不是则搜索接收功率最小的第二FA; 将第二阈值与所述第二FA的接收功率进行比较; 以及如果所接收的功率小于所述第二阈值，则在所述第二FA中分配业务信道，如果不是则拒绝所述请求。

公开(公告)号：US20060079057A1

公开(公告)日：2006-04-13

申请号：US11125101

申请日：2005-05-10

Applicant: Won-ju Cho ,  Chang-geun Ahn ,  Ki-ju Im ,  Jong-heon Yang ,  In-bok Baek ,  Seong-jae Lee

Inventor： Won-ju Cho ,  Chang-geun Ahn ,  Ki-ju Im ,  Jong-heon Yang ,  In-bok Baek ,  Seong-jae Lee

IPC: H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7834

Abstract: Provided are a field effect transistor and a method of fabricating the same, wherein the field effect transistor is formed which has a hyperfine channel length by employing a technique for forming a sidewall spacer and adjusting the deposition thickness of a thin film. In the field effect transistor of the present invention, a source junction and a drain junction are thin, and the overlap between the source and the gate and between the drain and the gate is prevented, thereby lowering parasitic resistance. Further, the gate electric field is easily introduced to the drain extending region, so that the carrier concentration is effectively controlled in the channel at the drain. Also, the drain extending region is formed to be thinner than the source, so that the short channel characteristic is excellent.

公开(公告)号：US07005356B2

公开(公告)日：2006-02-28

申请号：US10746493

申请日：2003-12-23

Applicant: Woo Seok Cheong ,  Seong Jae Lee ,  Moon Gyu Jang

Inventor： Woo Seok Cheong ,  Seong Jae Lee ,  Moon Gyu Jang

IPC: H01L21/28

CPC classification number: H01L21/28114 ,  H01L21/28123 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/66643 ,  H01L29/7839 ,  H01L29/78654

Abstract: A schottky barrier transistor and a method of manufacturing the same are provided. The method includes forming a gate insulating layer and a gate on a substrate, forming a spacer on a sidewall of the gate, and growing a polycrystalline silicon layer and a monocrystalline silicon layer on the gate and the substrate, respectively, using a selective silicon growth. A metal is deposited on the polycrystalline silicon layer and the monocrystalline silicon layer. Then, the metal reacts with silicon of the polycrystalline silicon layer and the monocyrstalline silicon layer to form a self-aligned metal silicide layer. Therefore, selective wet etching for removing an unreacted metal after silicidation can be omitted. Furthermore, etching damage caused during the formation of the spacer can be decreased during the growth of the monocrystalline silicon layer, thereby improving the electrical characteristics of devices.

Abstract translation: 提供肖特基势垒晶体管及其制造方法。 该方法包括在衬底上形成栅极绝缘层和栅极，在栅极的侧壁上形成间隔物，并使用选择性硅生长分别在栅极和衬底上生长多晶硅层和单晶硅层 。 金属沉积在多晶硅层和单晶硅层上。 然后，金属与多晶硅层和单晶硅层的硅反应形成自对准的金属硅化物层。 因此，可以省略用于除去硅化后的未反应金属的选择性湿法蚀刻。 此外，在单晶硅层的生长期间，可以减少在间隔物形成期间引起的蚀刻损伤，从而提高器件的电气特性。

公开(公告)号：US06797629B2

公开(公告)日：2004-09-28

申请号：US10185104

申请日：2002-06-27

Applicant: Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

Inventor： Moon Gyu Jang ,  Won Ju Cho ,  Seong Jae Lee ,  Kyoung Wan Park

IPC: H01L21302

CPC classification number: H01L29/78648 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78654

Abstract: The present invention relates to a method of manufacturing a nano transistor. The present invention manufactures the nano transistor without changing a conventional method of forming the nano transistor formed on a SOI substrate. Further, the present invention includes forming a N well and a P well at giving regions of an underlying silicon substrate so that a given voltage can be individually applied to a NMOS transistor and a PMOS transistor. Therefore, the present invention can control the threshold voltage to prevent an increase of the leakage current.

Abstract translation: 本发明涉及纳米晶体管的制造方法。 本发明制造纳米晶体管而不改变形成在SOI衬底上的纳米晶体管的常规方法。 此外，本发明包括在给定下面的硅衬底的区域上形成N阱和P阱，使得可以将给定的电压单独地施加到NMOS晶体管和PMOS晶体管。 因此，本发明可以控制阈值电压以防止漏电流的增加。

公开(公告)号：US06323504B1

公开(公告)日：2001-11-27

申请号：US09495740

申请日：2000-02-01

Applicant: Min Cheol Shin ,  Seong Jae Lee ,  Kyoung Wan Park

Inventor： Min Cheol Shin ,  Seong Jae Lee ,  Kyoung Wan Park

IPC: H01L2906

CPC classification number: B82Y10/00 ,  G11C2216/08 ,  H01L29/7888 ,  Y10S977/937

Abstract: A single-electron memory device using the electron-hole Coulomb blockade is provided. A single-electron memory device in accordance with an embodiment of the present invention includes a plurality of quantum dot tunnel-junction arrays, a gate electrode, and source and drain electrodes. The plurality of quantum dot tunnel-junction arrays include at least two tunnel-junctions, are parallelly coupled to each other, and are well separated from each other to prevent single-electron tunneling between them. One of the plurality of quantum dot tunnel-junction arrays includes the gate electrode, and the voltage applied to the gate electrode can vary the number of electron-hole pairs. Each of the above-mentioned plurality of quantum dot tunnel-junction arrays includes separate source and drain electrodes where voltages are applied

Abstract translation: 提供了使用电子孔库仑封锁的单电子存储器件。 根据本发明的实施例的单电子存储器件包括多个量子点隧道结阵列，栅电极和源电极和漏电极。 多个量子点隧道结阵列包括至少两个隧道结，它们彼此平行地耦合，并且彼此相互分离以防止它们之间的单电子隧穿。 多个量子点隧道结阵列中的一个包括栅电极，并且施加到栅电极的电压可以改变电子 - 空穴对的数量。 上述多个量子点隧道结阵列中的每一个包括分别施加电压的源极和漏极