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    Wavy micro gas chromatography column
    91.
    发明申请
    Wavy micro gas chromatography column 有权
    波浪微气相色谱柱

    公开(公告)号：US20160266073A1

    公开(公告)日：2016-09-15

    申请号：US15164841

    申请日：2016-05-25

    Applicant: University of Electronic Science and Technology of China

    Inventor： Xiaosong Du ,  Huan Yuan ,  Xulan Zhao ,  Penglin Wu ,  Yadong Jiang

    IPC: G01N30/02

    CPC classification number: G01N30/6086 ,  G01N30/6095 ,  G01N2030/025 ,  G01N2030/6056

    Abstract: A wavy micro gas chromatography column includes a silicon substrate and a bonded glass cover. A micro channel having a rectangular cross section is etched on the silicon substrate and coated with a stationary phase film. A projection figure of the micro channel on the silicon substrate includes multiple regular wavy curves. Each wavy curve is formed through alternately connecting first upper arcs with first lower arcs. Because the groove has a curving structure, the carrier gas velocity is decreased as the increase of the arc angle, resulting in an improvement of the flow uniformity at the zones between two adjacent bends but also an enlarging nonsymmetric distribution at the bends. Thus, an optimal curving structure can make the overall flow more even, and in turn achieve a better separation performance compared to the straight channel columns. Meanwhile, a wavy channel realizes a longer column length on a given area.

    Abstract translation: 波浪微气相色谱柱包括硅衬底和粘合玻璃罩。 在硅衬底上蚀刻具有矩形横截面的微通道并涂覆有固定相膜。 硅衬底上的微通道的投影图包括多个规则的波浪曲线。 每个波浪曲线通过交替地将第一上部弧线与第一个较低的弧线交替地形成。 由于凹槽具有弯曲结构，所以载气速度随着弧角的增加而减小，导致两个相邻弯头之间的区域的流动均匀性得到改善，而且在弯曲处也是扩大的非对称分布。 因此，与直通柱相比，最佳弯曲结构可以使整体流动更均匀，从而达到更好的分离性能。 同时，波浪通道在给定区域实现更长的列长度。

    Method for accessing internet via a vehicle network
    92.
    发明授权
    Method for accessing internet via a vehicle network 有权
    通过车辆网络访问互联网的方法

    公开(公告)号：US09391891B2

    公开(公告)日：2016-07-12

    申请号：US14521833

    申请日：2014-10-23

    Applicant: University of Electronic Science and Technology of China

    Inventor： Dan Liao ,  Gang Sun ,  Du Xu ,  Hongfang Yu ,  Bing Qiu ,  Peng Zhao

    IPC: H04L12/28 ,  H04L12/56 ,  H04L12/715 ,  H04L12/64 ,  H04L29/12

    CPC classification number: H04L45/741 ,  H04L12/6418 ,  H04L45/04 ,  H04L61/2015 ,  H04L61/2514

    Abstract: The present invention provides a method for accessing internet via a vehicle network. Vehicle terminal equipment can access OBU by means of the wireless AP on OBU, and realize the mutual communication with internet with the help of VANET network composed by OBU and RSU. Not only the normal communication between the OBU and RSU is guaranteed, but also the communication between vehicle terminal equipment and internet can be realized. Moreover, the present invention has the characteristics of anti-interference, convenience and real-time performance, and can adapt to the demand of the current network.

    Abstract translation: 本发明提供了一种经由车辆网络访问因特网的方法。 车载终端设备可以通过OBU上的无线AP访问OBU，并通过由OBU和RSU组成的VANET网络实现与互联网的相互通信。 不仅保证了OBU和RSU之间的正常通信，而且可以实现车载终端设备与互联网之间的通信。 此外，本发明具有抗干扰，方便实时的特点，可以适应当前网络的需求。

    Lateral power device having low specific on-resistance and using high-dielectric constant socket structure and manufacturing method therefor
    93.
    发明授权
    Lateral power device having low specific on-resistance and using high-dielectric constant socket structure and manufacturing method therefor 有权
    具有低比导通电阻和使用高介电常数插座结构的侧向功率器件及其制造方法

    公开(公告)号：US09324855B2

    公开(公告)日：2016-04-26

    申请号：US14650176

    申请日：2013-12-19

    Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

    Inventor： Junhong Li ,  Ping Li

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/06

    CPC classification number: H01L29/7802 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/66712 ,  H01L29/7812 ,  H01L29/7816

    Abstract: Provided is a lateral power device having low specific ON-resistance and using a high-dielectric constant socket structure and a manufacturing method therefor, which relate to semiconductor power devices. A source electrode (8) of the device is of a first conduction type, and a channel region (6), a silicon substrate (4) and an ohmic contact heavily-doped region are of a second conduction type; at least two isolation regions are arranged in an embedded manner in a drift region (1); between the isolation regions are the drift region (1) and the channel region (6); each isolation region extends from the source electrode (8) to a drain electrode (11); high-dielectric constant material strips (3) and first insulation dielectric layers (10) form boundaries of the bottoms and sidewalls of the isolation regions; the isolation regions are filled with a first filling material (2), a second insulation dielectric layer (9) is arranged on the upper surface of the drift region (1) and the upper surfaces of the isolation regions, and a gate electrode (5) directly contacts the first filling material (2) via holes on the second insulation dielectric layer (9); and a source electrode lead-out wire (16) and a drain electrode lead-out wire (12) directly contact the source electrode (8) and the drain electrode (11) respectively via the holes on the second insulation dielectric layer (9). The area of a power device can be greatly reduced on the premise of not reducing the withstand voltage and not increasing the specific ON-resistance.

    Abstract translation: 本发明提供一种具有低比导通电阻和使用涉及半导体功率器件的高介电常数插座结构及其制造方法的侧向功率器件。 器件的源极（8）是第一导电类型，沟道区（6），硅衬底（4）和欧姆接触重掺杂区是第二导电类型; 至少两个隔离区域以嵌入的方式布置在漂移区域（1）中; 在隔离区之间是漂移区（1）和沟道区（6）; 每个隔离区域从源电极（8）延伸到漏电极（11）; 高介电常数材料条（3）和第一绝缘电介质层（10）形成隔离区的底部和侧壁的边界; 隔离区域填充有第一填充材料（2），在漂移区域（1）的上表面和隔离区域的上表面上设置第二绝缘电介质层（9）和栅电极（5） ）通过第二绝缘介电层（9）上的孔直接接触第一填充材料（2）; 并且源电极引出线（16）和漏电极引出线（12）分别经由第二绝缘介电层（9）上的孔直接接触源电极（8）和漏电极（11） 。 在不降低耐压且不增加特定导通电阻的前提下，功率器件的面积可以大大降低。

    Readout circuit for uncooled infrared focal plane array
    94.
    发明授权
    Readout circuit for uncooled infrared focal plane array 有权

    公开(公告)号：US09163996B2

    公开(公告)日：2015-10-20

    申请号：US14298920

    申请日：2014-06-08

    Applicant: University of Electronic Science and Technology of China

    Inventor： Jian Lv ,  Longcheng Que ,  Yun Zhou ,  Linhai Wei ,  Yadong Jiang

    IPC: G01J5/00 ,  G01J5/10 ,  G01J5/22 ,  G01J5/20

    CPC classification number: G01J5/10 ,  G01J5/20 ,  G01J5/22 ,  G01J2005/106 ,  H04N5/33 ,  H04N5/3651

    Abstract: A readout circuit for an uncooled infrared focal plane array includes: a first biasing circuit for generating a detection output signal; a second biasing circuit for generating a first reference output signal; a first integration circuit; and an analog-to-digital circuit including: a ramp signal generating circuit for generating a ramp signal according to a second reference microbolometer of a third biasing circuit. In the readout circuit, subtracting and amplifying the detection output signal and the first reference output signal are provided by the integrator at an analog domain, while ratio counting is provided by an analog-to-digital converter during analog-to-digital conversion. Furthermore, a column level integrated readout channel utilizes only one reference microbolometer, and the chip level ramp signal generator also utilizes only one reference microbolometer. Therefore, a chip area is further saved, and noise sources are decreased.

    ULTRA LOW-POWER PIPELINED PROCESSOR
    95.
    发明申请
    ULTRA LOW-POWER PIPELINED PROCESSOR 有权
    超低功率流水线加工机

    公开(公告)号：US20140304572A1

    公开(公告)日：2014-10-09

    申请号：US13929758

    申请日：2013-06-27

    Applicant: University of Electronic Science and Technology of China

    Inventor： Yajuan HE ,  Tingting XIA ,  Tao LUO ,  Wubing GAN ,  Bo ZHANG

    IPC: G06F11/25

    CPC classification number: G01R31/317 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/3869 ,  Y02D10/152 ,  Y02D10/172

    Abstract: A pipelined processor including a combinational logic of several stages, a voltage regulator, a counter, a comparator, and a plurality of stage registers. Each stage register is disposed between two adjacent stages of the combinational logic. The stage register includes a flip-flop, a latch, an XOR gate, and a MUX module. When the high level of a register clock is coming, the flip-flop latches first data at the rising edge, and the latch receives second data during the high level. The data latched by the flip-flop and the latch respectively are compared by the XOR gate. If they are same, the output Error of the XOR gate is low level, and the output of the flip-flop is delivered to the next stage. Otherwise, the output Error of the XOR gate is high level, and the output of the latch is delivered to the next stage.

    Abstract translation: 一种流水线处理器，包括几级的组合逻辑，电压调节器，计数器，比较器和多个级寄存器。 每个级寄存器被布置在组合逻辑的两个相邻级之间。 级寄存器包括触发器，锁存器，异或门和MUX模块。 当寄存器时钟的高电平到来时，触发器在上升沿锁存第一数据，并且锁存器在高电平期间接收第二数据。 由触发器和锁存器锁存的数据分别由XOR门进行比较。 如果它们相同，则XOR门的输出误差为低电平，触发器的输出被传送到下一级。 否则，异或门的输出误差为高电平，并将锁存器的输出传送到下一级。

    FEDERATED LARGE MODEL ADAPTIVE LEARNING SYSTEM
    97.
    发明申请
    FEDERATED LARGE MODEL ADAPTIVE LEARNING SYSTEM 有权

    公开(公告)号：US20250103952A1

    公开(公告)日：2025-03-27

    申请号：US18521883

    申请日：2023-11-28

    Applicant: Hebei University of Technology ,  Zhejiang Lab ,  Shenzhen Institute for Advanced Study, University of Electronic Science and Technology of China ,  DALIAN UNIVERSITY OF TECHNOLOGY

    Inventor： Bin CAO ,  Zeyu JIANG ,  Xin LIU ,  Wen CHENG ,  Yun LI ,  Rensheng SHEN ,  Yuchun CHANG

    IPC: G06N20/00

    Abstract: The present invention provides a federated large model adaptive learning system. Based on the combination of multiobjective optimization and incremental learning, multiple optimization indexes are constructed, and adaptive mini model incremental learning is designed. A gradient scaling method of mini models is proposed for data privacy protection under federated learning, to make full use of gradient information. A correlation between the generalization ability and sampling data is revealed to propose a generalization ability evaluation function. With respect to the real problems of performance degradation and fault faced by industrial equipment during operation, multiple optimization objectives are designed in combination with the generalization ability evaluation function, and the models are updated and repaired adaptively through multiobjective evolutionary learning, to improve the usability of large models in real industrial scenarios. Finally, the adaptive accurate update of the large models and mini models is realized to improve the generalization ability of the models.

    POWER SEMICONDUCTOR DEVICE
    98.
    发明申请
    POWER SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250081553A1

    公开(公告)日：2025-03-06

    申请号：US18388870

    申请日：2023-11-13

    Applicant: University of Electronic Science and Technology of China

    Inventor： Ming QIAO ,  Jue LI ,  Zesheng SHI ,  Daoming SHEN ,  Bo ZHANG

    IPC: H01L29/06

    Abstract: A power semiconductor device, including a cell region, a transition region, and a terminal region. The transition region is located between the cell region and the terminal region of the device. A first conduction type substrate, a first conduction type epitaxial layer located above the first conduction type substrate, and a first conduction type buffer layer located in the first conduction type epitaxial layer are jointly arranged at the bottoms of the cell region, the transition region, and the terminal region of the device. In a high-current application, since the cell region occupies the largest area of a chip, in a case that breakdown can occur in the cell region and the current can be discharged through the cell region. On the basis of ensuring the BV of the terminal region, a silicon layer step is formed by elevating the position of a top structure of the terminal region.

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