公开(公告)号：US07732054B2

公开(公告)日：2010-06-08

申请号：US11966552

申请日：2007-12-28

Applicant: Young Hwan Kim ,  Woon Jo Cho ,  Seong Kim, II ,  Chun Keun Kim ,  Yong Tae Kim

Inventor： Young Hwan Kim ,  Woon Jo Cho ,  Seong Kim, II ,  Chun Keun Kim ,  Yong Tae Kim

IPC: B32B9/04 ,  B32B13/04 ,  B32B9/00 ,  H01L29/10

CPC classification number: C30B29/60 ,  C30B29/16 ,  Y10S977/774 ,  Y10T428/259

Abstract: A method for preparing a ZnO nanocrystal directly on a silicon substrate includes the steps of: (S1) forming a Zn—Si—O composite thin film on the silicon substrate; and (S2) thermally treating the obtained thin film. Particularly, ZnO nanocrystals are formed in an amorphous Zn—Si—O composite thin film by controlling the composition of the Zn—Si—O composite thin film and heating temperature thereof. With the present invention method for preparing a ZnO nanocrystal directly on a silicon substrate, more possibilities are opened up for the applications of ZnO nanocrystals to an optoelectronic device in use of a silicon substrate.

Abstract translation: 直接在硅衬底上制备ZnO纳米晶体的方法包括以下步骤：（S1）在硅衬底上形成Zn-Si-O复合薄膜; 和（S2）对所得薄膜进行热处理。 特别地，通过控制Zn-Si-O复合薄膜的组成和其加热温度，在非晶Zn-Si-O复合薄膜中形成ZnO纳米晶体。 利用本发明的用于在硅衬底上直接制备ZnO纳米晶体的方法，为了在使用硅衬底中将ZnO纳米晶体应用于光电子器件，开辟了更多的可能性。

公开(公告)号：US07729282B2

公开(公告)日：2010-06-01

申请号：US10558429

申请日：2003-07-07

Applicant: Koon-Seok Lee ,  Seung-Myun Baek ,  Hwan-Jong Choi ,  Yong-Tae Kim ,  Feel-Young Koo ,  Ja-In Koo ,  Seong-Hwan Kang

Inventor： Koon-Seok Lee ,  Seung-Myun Baek ,  Hwan-Jong Choi ,  Yong-Tae Kim ,  Feel-Young Koo ,  Ja-In Koo ,  Seong-Hwan Kang

IPC: H04L12/28

CPC classification number: H04L12/2825 ,  H04L12/2803 ,  H04L12/2818 ,  H04L43/00 ,  H04L43/0817 ,  H04L2012/2849

Abstract: The present invention discloses a configuration apparatus thereof which can efficiently configure a new home appliance in the home network system comprised of various home appliances. The configuration method of a home network system, comprising of confirming whether a previously-stored logical address is an initial logical address, transmitting a master search packet to the home network system when the logical address previously stored in the storage means is an initial logical address, waiting for a response packet from the home network system, when the response packet is received from the home network system, changing the initial logical address into a predetermined logical address according to reception of the response packet; and when the response packet is not received from the home network system, changing the previously-stored initial logical address into a previously-stored basic logical address.

Abstract translation: 本发明公开了一种可以在由各种家电组成的家庭网络系统中有效地配置新的家用电器的配置装置。 一种家庭网络系统的配置方法，包括：当先前存储的逻辑地址是初始逻辑地址时，确定先前存储的逻辑地址是否为初始逻辑地址，当先前存储在存储装置中的逻辑地址是初始逻辑地址时，将主搜索分组发送到家庭网络系统 当从家庭网络系统接收到响应分组时，等待来自家庭网络系统的响应分组，根据响应分组的接收将初始逻辑地址改变为预定的逻辑地址; 并且当没有从家庭网络系统接收到响应分组时，将先前存储的初始逻辑地址改变成先前存储的基本逻辑地址。

公开(公告)号：US20100103744A1

公开(公告)日：2010-04-29

申请号：US12588680

申请日：2009-10-23

Applicant: Seung-jin Yang ,  Jeong-uk Han ,  Yong-tae Kim ,  Yong-suk Choi ,  Bae-seong Kwon

Inventor： Seung-jin Yang ,  Jeong-uk Han ,  Yong-tae Kim ,  Yong-suk Choi ,  Bae-seong Kwon

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/0433

Abstract: A non-volatile memory device includes a memory cell array with a plurality of unit memory cells arranged in a matrix pattern, each of the unit memory cells having first and second non-volatile memory transistors sharing a common source, and a selection transistor connected between the common source and one of the first and second non-volatile memory transistors, a first word line coupled to control gates of the first non-volatile memory transistors arranged in a column direction of the memory cell array, a second word line coupled to control gates of the second non-volatile memory transistors arranged in the column direction of the memory cell array, a selection line coupled to gates of the selected transistors arranged in the column direction of the memory cell array, and at least one bit line coupled to drains of the first and second non-volatile memory transistors.

Abstract translation: 一种非易失性存储器件包括具有以矩阵模式布置的多个单元存储单元的存储单元阵列，每个单元存储单元具有共享公共源的第一和第二非易失性存储器晶体管，以及连接在 公共源和第一和第二非易失性存储器晶体管中的一个，耦合到以存储单元阵列的列方向布置的第一非易失性存储器晶体管的控制栅极的第一字线，耦合到控制的第二字线 布置在存储单元阵列的列方向上的第二非易失性存储晶体管的栅极，耦合到沿着存储单元阵列的列方向布置的所选晶体管的栅极的选择线以及耦合到漏极的至少一个位线 的第一和第二非易失性存储器晶体管。

公开(公告)号：US07706259B2

公开(公告)日：2010-04-27

申请号：US11635173

申请日：2006-12-07

Applicant: Yong Tae Kim ,  Sang Yeoun Lee ,  Kwang Suk Song ,  Bong Tae Kim

Inventor： Yong Tae Kim ,  Sang Yeoun Lee ,  Kwang Suk Song ,  Bong Tae Kim

IPC: H04L12/28

CPC classification number: H04L45/586 ,  H04L29/12028 ,  H04L49/552 ,  H04L61/103 ,  H04L69/40

Abstract: A method for implementing a redundant structure of an ATCA system via a base interface of a network system based on an ATCA standard, and the ATCA system for use in the same are disclosed. Each of routing protocol shelves and LI shelves includes two ports connected to two IPC paths provided from the base interface, such that a representative IP address is assigned to a single port to be used, performs IPC communication using the representative IP address. If a port error or link-down state occurs, the representative IP address is assigned to the other port, resulting in the implementation of stable IPC communication. If the port error or link-down state occurs in an active-mode ShMC shelf, an IPC path passing through a standby-mode ShMC shelf is provided.

Abstract translation: 公开了一种通过基于ATCA标准的网络系统的基本接口实现ATCA系统的冗余结构的方法和用于其中的ATCA系统。 每个路由协议货架和LI货架包括连接到从基本接口提供的两个IPC路径的两个端口，使得代表性IP地址被分配给要使用的单个端口，使用代表性IP地址执行IPC通信。 如果出现端口错误或链路关闭状态，则代表IP地址被分配给其他端口，从而实现稳定的IPC通信。 如果端口错误或链路状态发生在主动模式ShMC机架中，则提供通过待机模式ShMC机架的IPC路径。

公开(公告)号：US20100027770A1

公开(公告)日：2010-02-04

申请号：US12432111

申请日：2009-04-29

Applicant: Hyung Jun PARK ,  Hae Yong Kang ,  Young Soo Kim ,  Si Moon Jeon ,  Koon Seok Lee ,  Yong Tae Kim ,  Hyun Sang Kim ,  Eui Hyeok Kwon

Inventor： Hyung Jun PARK ,  Hae Yong Kang ,  Young Soo Kim ,  Si Moon Jeon ,  Koon Seok Lee ,  Yong Tae Kim ,  Hyun Sang Kim ,  Eui Hyeok Kwon

IPC: H04M11/00 ,  G08B3/00

CPC classification number: H04L12/2825 ,  H04B11/00 ,  H04L2012/285

Abstract: A home appliance system and an operation method thereof are disclosed. The home appliance outputs product information as a predetermined sound and transmits the sound through a connected communication network, thereby making it easier for a service center at a remote place to check a status of the home appliance. Further, the home appliance system and operation method thereof prevents noise or signal error generated in the procedure of converting product information into a signal of a predetermined frequency band in order to output the product information as a sound, thus enabling stable signal conversion and improving the accuracy of information transmission using the output of sound.

Abstract translation: 公开了家电系统及其操作方法。 家用电器将产品信息作为预定声音输出，并通过连接的通信网络发送声音，从而使远程位置的服务中心更容易地检查家用电器的状态。 此外，家用电器系统及其操作方法防止将产品信息转换为预定频带的信号的过程中产生的噪声或信号错误，以便将产品信息输出为声音，从而实现稳定的信号转换和改善 使用声音输出的信息传输精度。

公开(公告)号：US20090219282A1

公开(公告)日：2009-09-03

申请号：US12266870

申请日：2008-11-07

Applicant: Yong-tae KIM ,  Jae-yeon SONG ,  Gun-ill LEE ,  Seo-young HWANG ,  Dae-sik KIM ,  Jae-seung KIM

Inventor： Yong-tae KIM ,  Jae-yeon SONG ,  Gun-ill LEE ,  Seo-young HWANG ,  Dae-sik KIM ,  Jae-seung KIM

IPC: G06T15/00 ,  H04N7/26

CPC classification number: H04N19/597 ,  H04N19/50

Abstract: Provided are a method and apparatus for encoding and decoding a datastream into which multiview image information is inserted. The method of decoding a multiview image datastream includes extracting multiview image information including information on at least one view image of a multiview image, from at least one elementary stream of the multiview image datastream; extracting a multiview image parameter regarding the multiview image based on the number of elementary streams and a correlation between view images of the multiview image; and restoring the multiview image by using the extracted multiview image parameter and the extracted multiview image information.

Abstract translation: 提供了一种用于对数据流进行编码和解码的方法和装置，其中插入有多视图图像信息。 解码多视图图像数据流的方法包括从多视点图像数据流的至少一个基本流中提取包括关于多视图图像的至少一个视图图像的信息的多视图图像信息; 基于基本流的数量和多视图图像的观看图像之间的相关性提取关于多视图图像的多视图图像参数; 以及通过使用提取的多视图图像参数和所提取的多视图图像信息来恢复多视图图像。

公开(公告)号：US07581234B2

公开(公告)日：2009-08-25

申请号：US11416316

申请日：2006-05-03

Applicant: Yong Tae Kim

Inventor： Yong Tae Kim

IPC: G11B17/028

CPC classification number: G11B17/0282

Abstract: Provided is turntable assembly of a spindle motor. The turntable assembly includes a turntable and a back yoke. The back yoke is installed on the turntable. The turntable includes at least one of a turntable coupling protrusion and a protrusion coupler formed thereon. The back yoke includes at least one of a protrusion coupler and a coupling protrusion formed thereon to face the corresponding components formed on the turntable. The coupling protrusion is inserted in the protrusion coupler to fix the back yoke to the turntable.

Abstract translation: 提供主轴电动机的转盘组件。 转盘组件包括转盘和后轭。 后轭安装在转台上。 转台包括转盘联接突起和形成在其上的突起联接件中的至少一个。 后轭包括突起联接器和形成在其上的耦合突起中的至少一个，以面对形成在转台上的相应部件。 联接突起插入到突起联接器中，以将后轭固定到转台上。

公开(公告)号：US07492000B2

公开(公告)日：2009-02-17

申请号：US11444369

申请日：2006-06-01

Applicant: Hee Seog Jeon ,  Seung Beom Yoon ,  Yong Tae Kim

Inventor： Hee Seog Jeon ,  Seung Beom Yoon ,  Yong Tae Kim

IPC: H01L29/94

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

Abstract: Provided are non-volatile split-gate memory cells having self-aligned floating gate and the control gate structures and exemplary processes for manufacturing such memory cells that provide improved dimensional control over the relative lengths and separation of the split-gate elements. Each control gate includes a projecting portion that extends over at least a portion of the associated floating gate with the size of the projecting portion being determined by a first sacrificial polysilicon spacer that, when removed, produces a concave region in an intermediate insulating structure. The control gate is then formed as a polysilicon spacer adjacent the intermediate insulating structure, the portion of the spacer extending into the concave region determining the dimension and spacing of the projecting portion and the thickness of the interpoly oxide (IPO) separating the upper portions of the split-gate electrodes thereby providing improved performance and manufacturability.

Abstract translation: 提供了具有自对准浮动栅极的非易失性分裂栅极存储器单元以及用于制造这样的存储单元的控制栅极结构和示例性工艺，其提供了分离栅极元件的相对长度和间隔的改进的尺寸控制。 每个控制门包括突出部分，该突出部分在相关联的浮动栅极的至少一部分上延伸，突出部分的尺寸由第一牺牲多晶硅间隔物确定，当被去除时，其在中间绝缘结构中产生凹入区域。 然后，控制栅极形成为与中间绝缘结构相邻的多晶硅间隔物，间隔物的延伸到凹区中的部分确定突出部分的尺寸和间距以及分离上部的多晶硅氧化物（IPO）的厚度 因此分裂栅电极提供了改进的性能和可制造性。

公开(公告)号：US07465988B2

公开(公告)日：2008-12-16

申请号：US11871876

申请日：2007-10-12

Applicant: Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

Inventor： Sung-Sam Lee ,  Yong-Tae Kim ,  Mi-Youn Kim ,  Gyo-Young Jin ,  Dae-Won Ha ,  Yun-Gi Kim

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L21/823437 ,  H01L21/823481

Abstract: A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

Abstract translation: 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20080268592A1

公开(公告)日：2008-10-30

申请号：US12004698

申请日：2007-12-21

Applicant: Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

Inventor： Weon-Ho Park ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC: H01L21/8242

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/66825 ,  H01L29/7881

Abstract: Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.

Abstract translation: 提供一种闪速存储器件及其制造方法。 该方法包括在半导体衬底的有源区上形成第一电介质层。 在具有第一介电层的半导体衬底上形成第一导电层。 在第一导电层上形成掩模图案。 使用掩模图案作为蚀刻掩模，蚀刻第一导电层以形成从其上表面向其中间部分变窄的第一导电图案。 在具有第一导电图案的半导体衬底上形成第二电介质层。 在具有第二介电层的半导体衬底上形成与第一导电图案相邻的有源区域交叉并部分覆盖第一导电图案的第二导电图案。