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114 条记录 (耗时 0.026 秒)

    Using Epoch Counter Values for Controlling the Retention of Cache Blocks in a Cache
    93.
    发明申请
    Using Epoch Counter Values for Controlling the Retention of Cache Blocks in a Cache 有权

    公开(公告)号：US20230095461A1

    公开(公告)日：2023-03-30

    申请号：US17491478

    申请日：2021-09-30

    申请人： Advanced Micro Devices, Inc.

    发明人： Nuwan Jayasena

    IPC分类号： G06F12/0802

    摘要： An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.

    APPROACH FOR REDUCING SIDE EFFECTS OF COMPUTATION OFFLOAD TO MEMORY
    94.
    发明申请
    APPROACH FOR REDUCING SIDE EFFECTS OF COMPUTATION OFFLOAD TO MEMORY 有权

    公开(公告)号：US20230004491A1

    公开(公告)日：2023-01-05

    申请号：US17364854

    申请日：2021-06-30

    申请人： Advanced Micro Devices, Inc.

    发明人： Shaizeen Aga ,  Nuwan Jayasena

    IPC分类号： G06F12/084 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/02

    摘要： A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.

    SEMI-SORTING COMPRESSION WITH ENCODING AND DECODING TABLES
    95.
    发明申请
    SEMI-SORTING COMPRESSION WITH ENCODING AND DECODING TABLES 有权

    公开(公告)号：US20220239315A1

    公开(公告)日：2022-07-28

    申请号：US17722931

    申请日：2022-04-18

    申请人： Advanced Micro Devices, Inc.

    发明人： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

    IPC分类号： H03M7/40 ,  G06F7/08 ,  G06F3/06

    摘要： A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

    ADDRESS MAPPING-AWARE TASKING MECHANISM
    97.
    发明申请
    ADDRESS MAPPING-AWARE TASKING MECHANISM 有权

    公开(公告)号：US20220206839A1

    公开(公告)日：2022-06-30

    申请号：US17135381

    申请日：2020-12-28

    申请人： Advanced Micro Devices, Inc.

    发明人： Jonathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

    IPC分类号： G06F9/48 ,  G06F3/06

    摘要： An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.

    HARDWARE-SOFTWARE COLLABORATIVE ADDRESS MAPPING SCHEME FOR EFFICIENT PROCESSING-IN-MEMORY SYSTEMS
    98.
    发明申请
    HARDWARE-SOFTWARE COLLABORATIVE ADDRESS MAPPING SCHEME FOR EFFICIENT PROCESSING-IN-MEMORY SYSTEMS 有权

    公开(公告)号：US20220066662A1

    公开(公告)日：2022-03-03

    申请号：US17006646

    申请日：2020-08-28

    申请人： Advanced Micro Devices, Inc.

    发明人： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

    IPC分类号： G06F3/06

    摘要： Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

    COMMAND THROUGHPUT IN PIM-ENABLED MEMORY USING AVAILABLE DATA BUS BANDWIDTH
    99.
    发明申请
    COMMAND THROUGHPUT IN PIM-ENABLED MEMORY USING AVAILABLE DATA BUS BANDWIDTH 有权

    公开(公告)号：US20210373805A1

    公开(公告)日：2021-12-02

    申请号：US16885677

    申请日：2020-05-28

    申请人： Advanced Micro Devices, Inc.

    发明人： Johnathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

    IPC分类号： G06F3/06

    摘要： An approach is provided for reducing command bus traffic between memory controllers and PIM-enabled memory modules using special PIM commands. The term “special PIM command” is used herein to describe embodiments and refers to a PIM command for which the corresponding module-specific command information is provided to memory modules via a non-command bus data path. A memory controller generates and issues a special PIM command to multiple PIM-enabled memory modules via a command bus and provides module-specific command information (e.g., address information) for the special PIM command to the PIM-enabled memory modules via the non-command bus data path that is shared by the PIM-enabled memory modules and the memory controller.

    Locality-aware and sharing-aware cache coherence for collections of processors
    100.
    发明授权
    Locality-aware and sharing-aware cache coherence for collections of processors 有权

    公开(公告)号：US11119923B2

    公开(公告)日：2021-09-14

    申请号：US15440979

    申请日：2017-02-23

    申请人： Advanced Micro Devices, Inc.

    发明人： Amin Farmahini Farahani ,  Nuwan Jayasena

    IPC分类号： G06F3/06 ,  G06F12/00 ,  G06F13/00 ,  G06F12/0813 ,  G06F12/0837 ,  G06F12/0811

    摘要： A cache coherence technique for operating a multi-processor system including shared memory includes allocating a cache line of a cache memory of a processor to a memory address in the shared memory in response to execution of an instruction of a program executing on the processor. The technique includes encoding a shared information state of the cache line to indicate whether the memory address is a shared memory address shared by the processor and a second processor, or a private memory address private to the processor, in response to whether the instruction is included in a critical section of the program, the critical section being a portion of the program that confines access to shared, writeable data.