公开(公告)号：US11875425B2

公开(公告)日：2024-01-16

申请号：US17134904

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Sooraj Puthoor ,  Bradford Beckmann ,  Nuwan Jayasena ,  Anthony Gutierrez

IPC: G06F9/38 ,  G06T1/20 ,  G06F9/30 ,  G06F9/54

CPC classification number: G06T1/20 ,  G06F9/30036 ,  G06F9/3836 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/545 ,  G06T2210/52

Abstract: Implementing heterogeneous wavefronts on a graphics processing unit (GPU) is disclosed. A scheduler assigns heterogeneous wavefronts for execution on a compute unit of a processing device. The heterogeneous wavefronts include different types of wavefronts such as vector compute wavefronts and service-level wavefronts that vary in resource requirements and instruction sets. As one example, heterogeneous wavefronts may include scalar wavefronts and vector compute wavefronts that execute on scalar units and vector units, respectively. Distinct sets of instructions are executed for the heterogeneous wavefronts on the compute unit. Heterogeneous wavefronts are processed in the same pipeline of the processing device.

公开(公告)号：US11847061B2

公开(公告)日：2023-12-19

申请号：US17385783

申请日：2021-07-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  John Kalamatianos

IPC: G06F12/08 ,  G06F13/16 ,  G06F12/02 ,  G06F12/0891 ,  G06F12/0811

CPC classification number: G06F12/0891 ,  G06F12/0238 ,  G06F12/0811 ,  G06F13/1668

Abstract: A technical solution to the technical problem of how to support memory-centric operations on cached data uses a novel memory-centric memory operation that invokes write back functionality on cache controllers and memory controllers. The write back functionality enforces selective flushing of dirty, i.e., modified, cached data that is needed for memory-centric memory operations from caches to the completion level of the memory-centric memory operations, and updates the coherence state appropriately at each cache level. The technical solution ensures that commands to implement the selective cache flushing are ordered before the memory-centric memory operation at the completion level of the memory-centric memory operation.

公开(公告)号：US11847048B2

公开(公告)日：2023-12-19

申请号：US17031518

申请日：2020-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F12/02 ,  G06F12/0815 ,  G06F15/173 ,  G06F12/0868 ,  G06F12/084

CPC classification number: G06F12/0238 ,  G06F12/084 ,  G06F12/0815 ,  G06F12/0868 ,  G06F15/17331

Abstract: A processing device and methods of controlling remote persistent writes are provided. Methods include receiving an instruction of a program to issue a persistent write to remote memory. The methods also include logging an entry in a local domain when the persistent write instruction is received and providing a first indication that the persistent write will be persisted to the remote memory. The methods also include executing the persistent write to the remote memory and providing a second indication that the persistent write to the remote memory is completed. The methods also include providing the first and second indications when it is determined not to execute the persistent write according to global ordering and providing the second indication without providing the first indication when it is determined to execute the persistent write to remote memory according to global ordering.

公开(公告)号：US11797201B2

公开(公告)日：2023-10-24

申请号：US17745278

申请日：2022-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0673 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0607

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

公开(公告)号：US11742259B2

公开(公告)日：2023-08-29

申请号：US17353115

申请日：2021-06-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Manish Arora ,  Nuwan Jayasena

IPC: H01L23/427 ,  H05K1/02 ,  H01L23/00 ,  H05K3/46 ,  H05K3/34

CPC classification number: H01L23/4275 ,  H05K1/0203 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K3/3436 ,  H05K3/4697 ,  H01L2224/131 ,  H01L2924/014

Abstract: Various circuit board embodiments are disclosed. In one aspect, an apparatus is provided that includes a circuit board and a first phase change material pocket positioned on or in the circuit board and contacting a surface of the circuit board.

公开(公告)号：US20230095461A1

公开(公告)日：2023-03-30

申请号：US17491478

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena

IPC: G06F12/0802

Abstract: An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.

公开(公告)号：US20230004491A1

公开(公告)日：2023-01-05

申请号：US17364854

申请日：2021-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/02

Abstract: A technical solution to the technical problem of how to reduce the undesirable side effects of offloading computations to memory uses read hints to preload results of memory-side processing into a processor-side cache. A cache controller, in response to identifying a read hint in a memory-side processing instruction, causes results of the memory-side processing to be preloaded into a processor-side cache. Implementations include, without limitation, enabling or disabling the preloading based upon cache thrashing levels, preloading results, or portions of results, of memory-side processing to particular destination caches, preloading results based upon priority and/or degree of confidence, and/or during periods of low data bus and/or command bus utilization, last stores considerations, and enforcing an ordering constraint to ensure that preloading occurs after memory-side processing results are complete.

公开(公告)号：US20220239315A1

公开(公告)日：2022-07-28

申请号：US17722931

申请日：2022-04-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena ,  John Kalamatianos

IPC: H03M7/40 ,  G06F7/08 ,  G06F3/06

Abstract: A data processing platform, method, and program product perform compression and decompression of a set of data items. Suffix data and a prefix are selected for each respective data item in the set of data items based on data content of the respective data item. The set of data items is sorted based on the prefixes. The prefixes are encoded by querying multiple encoding tables to create a code word containing compressed information representing values of all prefixes for the set of data items. The code word and suffix data for each of the data items are stored in memory. The code word is decompressed to recover the prefixes. The recovered prefixes are paired with their respective suffix data.

公开(公告)号：US20220206899A1

公开(公告)日：2022-06-30

申请号：US17133843

申请日：2020-12-24

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Nuwan Jayasena ,  Sudhanva Gurumurthi ,  Shaizeen Aga ,  Shrikanth Ganapathy

IPC: G06F11/14 ,  G06F11/07 ,  G06F9/30 ,  G06F9/38

Abstract: Methods and processing devices are provided for error protection to support instruction replay for executing idempotent instructions at a processing in memory PIM device. The processing apparatus includes a PIM device configured to execute an idempotent instruction. The processing apparatus also includes a processor, in communication with the PIM device, configured to issue the idempotent instruction to the PIM device for execution at the PIM device and reissue the idempotent instruction to the PIM device when one of execution of the idempotent instruction at the PIM device results in an error and a predetermined latency period expires from when the idempotent instruction is issued.

公开(公告)号：US20220206839A1

公开(公告)日：2022-06-30

申请号：US17135381

申请日：2020-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Jonathan Alsop ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F9/48 ,  G06F3/06

Abstract: An Address Mapping-Aware Tasking (AMAT) mechanism manages compute task data and issues compute tasks on behalf of threads that created the compute task data. The AMAT mechanism stores compute task data generated by host threads in a set of partitions, where each partition is designated for a particular memory module. The AMAT mechanism maintains address mapping data that maps address information to partitions. Threads push compute task data to the AMAT mechanism instead of generating and issuing their own compute tasks. The AMAT mechanism uses address information included in the compute task data and the address mapping data to determine partitions in which to store the compute task data. The AMAT mechanism then issues compute tasks to be executed near the corresponding memory modules (i.e., in PIM execution units or NUMA compute nodes) based upon the compute task data stored in the partitions.