公开(公告)号：US07217647B2

公开(公告)日：2007-05-15

申请号：US10904330

申请日：2004-11-04

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/823468 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823475

摘要： Disclosed is a method of fabricating a field effect transistor. In the method, a gate stack on a top surface of a semiconductor substrate is formed, and then a first spacer is formed on a sidewall of the gate stack. Next, a silicide self-aligned to the first spacer is deposited in/or on the semiconductor substrate. Subsequently a second spacer covering the surface of the first spacer, and a contact liner over at least the gate stack, the second spacer and the silicide, are formed. Then an interlayer dielectric over the contact liner is deposited. Next, a metal contact opening is formed to expose the contact liner over the silicide. Finally, the opening is extended through the contact liner to expose the silicide without exposing the substrate.

摘要翻译： 公开了一种制造场效应晶体管的方法。 在该方法中，形成半导体衬底的顶表面上的栅极叠层，然后在栅极堆叠的侧壁上形成第一间隔物。 接下来，将与第一间隔物自对准的硅化物沉积在半导体衬底中的/或上。 随后，形成覆盖第一间隔物的表面的第二间隔物，以及至少栅极叠层，第二间隔物和硅化物之间的接触衬垫。 然后沉积接触衬垫上的层间电介质。 接下来，形成金属接触开口以使接触衬里暴露在硅化物上。 最后，将开口延伸穿过接触衬垫以暴露硅化物而不暴露衬底。

公开(公告)号：US06984564B1

公开(公告)日：2006-01-10

申请号：US10710184

申请日：2004-06-24

申请人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

发明人： Shih-Fen Huang ,  Clement Wann ,  Haining S. Yang

IPC分类号： H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/7842 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/7843

摘要： An SRAM in a CMOS integrated circuit is subjected to stress on the channels of its transistors; compressive stress on the pull-up and pass gate transistors and tensile stress on the pull-down transistors in a version designed to improve stability; and compressive stress on the pull-up transistors and tensile stress on the pull-down and pass gate transistors in a version designed to reduce the cell size and increase speed of operation.

摘要翻译： CMOS集成电路中的SRAM在其晶体管的沟道上受到应力; 上拉和栅极晶体管中的压应力和下拉晶体管中的拉伸应力，旨在提高稳定性; 并且上拉晶体管中的压应力和下拉和通过栅极晶体管中的拉伸应力在设计成减小电池尺寸并增加操作速度的版本中。

公开(公告)号：US06946709B2

公开(公告)日：2005-09-20

申请号：US10726326

申请日：2003-12-02

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/7843 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/0615 ,  H01L29/1083 ,  H01L29/6656

摘要： Disclosed is a method of forming an integrated circuit structure having first-type transistors, such as P-type field effect transistors (PFETs) and complementary second-type transistors, such as N-type field effect transistors (NFETs) on the same substrate. More specifically, the invention forms gate conductors above channel regions in the substrate, sidewall spacers adjacent the gate conductors, and source and drain extensions in the substrate. The sidewall spacers are larger (extend further from the gate conductor) in the PFETs than in the NFETs. The sidewall spacers align the source and drain extensions during the implanting process. Therefore, the larger sidewall spacers position (align) the source and drain implants further from the channel region for the PFETs when compared to the NFETs. Then, during the subsequent annealing processes, the faster moving PFET impurities will be restrained from diffusing too far into the channel region under the gate conductor. This prevents the short channel effect that occurs when the source and drain impurities extend too far beneath the gate conductor and short out the channel region.

公开(公告)号：US6002259A

公开(公告)日：1999-12-14

申请号：US8969

申请日：1998-01-20

申请人： Alfred J. Griffin, Jr. ,  Franz R. Brotzen ,  Daniel L. Callahan ,  Haining S. Yang

发明人： Alfred J. Griffin, Jr. ,  Franz R. Brotzen ,  Daniel L. Callahan ,  Haining S. Yang

IPC分类号： G01N3/00 ,  G01N19/04 ,  G01R27/26

CPC分类号： G01N19/04 ,  G01N2203/005

摘要： A electrostatic adhesion tester for thin film conductors. In one embodiment, a device is provided for testing the adhesion strength of a thin film conductor that has been formed upon a substrate. The device includes an adhesion tester that is primarily comprised of a conducting portion. The conducting portion is applied to the thin film conductor so that it does not physically contact the thin film conductor, but leaves a small space there between. A power supply may further be provided for coupling to either the adhesion tester, the thin film conductor, or both in order to create a potential difference between the conducting portion and the thin film conductor. The potential difference creates an electric field between the conducting portion and the thin film conductor that induces stress in the thin film conductor. A measuring device may also be provided for coupling to the adhesion tester and the thin film conductor in order to measure an electrical parameter of the electric field, which is indicative of the adhesion strength.

摘要翻译： 薄膜导体用静电粘合试验机。 在一个实施例中，提供了一种用于测试已经形成在基底上的薄膜导体的粘附强度的装置。 该装置包括主要由导电部分组成的粘合试验机。 导电部分被施加到薄膜导体，使得它不物理地接触薄膜导体，而在它们之间留下很小的空间。 为了在导电部分和薄膜导体之间产生电位差，可以进一步提供电源用于耦合到粘附测试仪，薄膜导体或两者。 电位差在导电部分和薄膜导体之间产生电场，引起薄膜导体中的应力。 还可以提供测量装置，用于耦合到粘合测试仪和薄膜导体，以测量电场的电参数，这表示粘合强度。

公开(公告)号：US09040960B2

公开(公告)日：2015-05-26

申请号：US13435994

申请日：2012-03-30

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/739

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TFET时，漏极区包括p掺杂的硅，而源区包括n掺杂的碳化硅。

公开(公告)号：US20140027851A1

公开(公告)日：2014-01-30

申请号：US13618240

申请日：2012-09-14

申请人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

发明人： Yue Tan ,  Zhibin Ren ,  Richard A. Wachnik ,  Haining S. Yang

IPC分类号： H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/7833 ,  H01L29/7841

摘要： Contact with a floating body of an FET in SOI may be formed in a portion of one of the two diffusions of the FET, wherein the portion of the diffusion (such as N−, for an NFET) which is “sacrificed” for making the contact is a portion of the diffusion which is not immediately adjacent (or under) the gate. This works well with linked body FETs, wherein the diffusion does not extend all the way to BOX, hence the linked body (such as P−) extends under the diffusion where the contact is being made. An example showing making contact for ground to two NFETs (PG and PD) of a 6T SRAM cell is shown.

摘要翻译： 与SOI中的FET的浮体接触可以形成在FET的两个扩散中的一个中的一个的一部分中，其中“牺牲”的扩散部分（例如N，用于NFET）用于制造 接触是不直接相邻（或在门下方）的扩散部分。 这与连接的主体FET工作良好，其中扩散不会一直延伸到BOX，因此连接体（例如P-）在形成接触的扩散下延伸。 示出了向6T SRAM单元的两个NFET（PG和PD）接地的示例。

公开(公告)号：US08513769B2

公开(公告)日：2013-08-20

申请号：US12765275

申请日：2010-04-22

申请人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

发明人： Charles T. Black ,  Matthew E. Colburn ,  Timothy J. Dalton ,  Daniel C. Edelstein ,  Wai-Kin Li ,  Anthony K. Stamper ,  Haining S. Yang

IPC分类号： H01L23/5256 ,  H01L23/5329 ,  H01L21/7682

CPC分类号： H01L23/5256 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76816 ,  H01L23/5226 ,  H01L23/5228 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： Electrical fuses and resistors having a sublithographic lateral or vertical dimension are provided. A conductive structure comprising a conductor or a semiconductor is formed on a semiconductor substrate. At least one insulator layer is formed on the conductive structure. A recessed area is formed in the at least one insulator layer. Self-assembling block copolymers are applied into the recessed area and annealed to form a fist set of polymer blocks and a second set of polymer blocks. The first set of polymer blocks are etched selective to the second set and the at least one insulator layer. Features having sublithographic dimensions are formed in the at least one insulator layer and/or the conductive structure. Various semiconductor structures having sublithographic dimensions are formed including electrical fuses and resistors.

摘要翻译： 提供具有亚光刻横向或垂直尺寸的电熔丝和电阻器。 包括导体或半导体的导电结构形成在半导体衬底上。 在导电结构上形成至少一个绝缘体层。 在所述至少一个绝缘体层中形成凹陷区域。 将自组装嵌段共聚物施加到凹陷区域中并退火以形成第一组聚合物嵌段和第二组聚合物嵌段。 第一组聚合物嵌段被选择性蚀刻到第二组和至少一个绝缘体层。 具有亚光刻尺寸的特征形成在至少一个绝缘体层和/或导电结构中。 形成具有亚光刻尺寸的各种半导体结构，其包括电熔丝和电阻器。

公开(公告)号：US08456006B2

公开(公告)日：2013-06-04

申请号：US13174841

申请日：2011-07-01

申请人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

发明人： Chih-Chao Yang ,  Thomas M. Shaw ,  Keith Kwong Hon Wong ,  Haining S. Yang

IPC分类号： H01L21/00

CPC分类号： H01L21/76841 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53271 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides an interconnect structure (of the single or dual damascene type) and a method of forming the same, in which a dense (i.e., non-porous) dielectric spacer is present on the sidewalls of a dielectric material. More specifically, the inventive structure includes a dielectric material having a conductive material embedded within at least one opening in the dielectric material, wherein the conductive material is laterally spaced apart from the dielectric material by a diffusion barrier, a dense dielectric spacer and, optionally, an air gap. The presence of the dense dielectric spacer results in a hybrid interconnect structure that has improved reliability and performance as compared with existing prior art interconnect structures which do not include such dense dielectric spacers. Moreover, the inventive hybrid interconnect structure provides for better process control which leads to the potential for high volume manufacturing.

摘要翻译： 本发明提供了一种互连结构（单镶嵌型或双镶嵌型）及其形成方法，其中在电介质材料的侧壁上存在致密的（即非多孔的）电介质间隔物。 更具体地，本发明的结构包括介电材料，其具有嵌入介电材料中的至少一个开口中的导电材料，其中导电材料通过扩散阻挡层，致密电介质间隔物和任选地， 气隙。 与现有技术的不包括这种致密电介质间隔物的互连结构相比，密集电介质间隔物的存在导致混合互连结构具有改进的可靠性和性能。 此外，本发明的混合互连结构提供了更好的过程控制，这导致了大批量制造的潜力。

公开(公告)号：US08405131B2

公开(公告)日：2013-03-26

申请号：US12342677

申请日：2008-12-23

申请人： Haining S. Yang

发明人： Haining S. Yang

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28052 ,  H01L21/823835 ,  H01L29/4933 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： The present invention relates to a semiconductor device that comprises at least one field effect transistor (FET) containing a source region, a drain region, a channel region, a gate dielectric layer, a gate electrode, and one or more gate sidewall spacers. The gate electrode of such an FET contains an intrinsically stressed gate metal silicide layer, which is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating stress in the channel region of the FET. Preferably, the semiconductor device comprises at least one p-channel FET, and more preferably, the p-channel FET has a gate electrode with an intrinsically stressed gate metal silicide layer that is laterally confined by one or more gate sidewall spacers and is arranged and constructed for creating compressive stress in the p-channel of the FET.

摘要翻译： 本发明涉及一种半导体器件，其包括至少一个包含源极区域，漏极区域，沟道区域，栅极介电层，栅极电极和一个或多个栅极侧壁间隔物的场效应晶体管（FET）。 这种FET的栅电极包含本征应力的栅极金属硅化物层，其被一个或多个栅极侧壁间隔物侧向限制，并且被布置和构造用于在FET的沟道区域中产生应力。 优选地，半导体器件包括至少一个p沟道FET，并且更优选地，p沟道FET具有栅极电极，其具有被一个或多个栅极侧壁间隔物侧向限制的本征应力栅极金属硅化物层， 构造用于在FET的p沟道中产生压应力。

公开(公告)号：US20120193679A1

公开(公告)日：2012-08-02

申请号：US13435994

申请日：2012-03-30

申请人： Xiangdong Chen ,  Haining S. Yang

发明人： Xiangdong Chen ,  Haining S. Yang

IPC分类号： H01L29/772

CPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7391

摘要： The present invention relates to a heterojunction tunneling effect transistor (TFET), which comprises spaced apart source and drain regions with a channel region located therebetween and a gate stack located over the channel region. The drain region comprises a first semiconductor material and is doped with a first dopant species of a first conductivity type. The source region comprises a second, different semiconductor material and is doped with a second dopant species of a second, different conductivity type. The gate stack comprises at least a gate dielectric and a gate conductor. When the heterojunction TFET is an n-channel TFET, the drain region comprises n-doped silicon, while the source region comprises p-doped silicon germanium. When the heterojunction TFET is a p-channel TFET, the drain region comprises p-doped silicon, while the source region comprises n-doped silicon carbide.

摘要翻译： 本发明涉及异质结隧道效应晶体管（TFET），其包括间隔开的源极和漏极区，其中位于其间的沟道区和位于沟道区上方的栅极叠层。 漏极区域包括第一半导体材料并且掺杂有第一导电类型的第一掺杂物种类。 源区包括第二不同的半导体材料，并且掺杂有第二不同导电类型的第二掺杂物种。 栅极堆叠至少包括栅极电介质和栅极导体。 当异质结TFET是n沟道TFET时，漏极区域包括n掺杂的硅，而源极区域包括p掺杂的硅锗。 当异质结TFET是p沟道TFET时，漏极区包括p掺杂的硅，而源区包括n掺杂的碳化硅。