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214 条记录 (耗时 0.021 秒)

    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE
    91.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K GATE STACKS FOR DEVICES OF DIFFERENT THRESHOLD VOLTAGE 有权
    用于不同阈值电压器件的高K栅极堆栈中的工作功能调整

    公开(公告)号：US20110127616A1

    公开(公告)日：2011-06-02

    申请号：US12905501

    申请日：2010-10-15

    申请人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    发明人： Jan Hoentschel ,  Sven Beyer ,  Thilo Scheiper

    IPC分类号： H01L27/088 ,  H01L21/336

    CPC分类号： H01L21/28176 ,  H01L21/823857 ,  H01L29/517

    摘要： In sophisticated semiconductor devices, different threshold voltage levels for transistors may be set in an early manufacturing stage, i.e., prior to patterning the gate electrode structures, by using multiple diffusion processes and/or gate dielectric materials. In this manner, substantially the same gate layer stacks, i.e., the same electrode materials and the same dielectric cap materials, may be used, thereby providing superior patterning uniformity when applying sophisticated etch strategies.

    摘要翻译： 在复杂的半导体器件中，可以在早期制造阶段，即在通过使用多个扩散工艺和/或栅极电介质材料图案化栅极电极结构之前，将晶体管的不同阈值电压电平设置。 以这种方式，可以使用基本相同的栅极层堆叠，即相同的电极材料和相同的电介质盖材料，从而在应用复杂的蚀刻策略时提供优异的图案均匀性。

    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same
    94.
    发明授权
    Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same 有权
    包括具有应力沟道区域的场效应晶体管的半导体结构及其形成方法

    公开(公告)号：US07608499B2

    公开(公告)日：2009-10-27

    申请号：US11685847

    申请日：2007-03-14

    申请人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    发明人： Karla Romero ,  Sven Beyer ,  Jan Hoentschel ,  Rolf Stephan

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823807 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7848

    摘要： A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a first transistor element and a second transistor element. Each of the first transistor element and the second transistor element comprises a gate electrode. A stressed material layer is deposited over the first transistor element and the second transistor element. The stressed material layer is processed to form from the stressed material layer sidewall spacers adjacent the gate electrode of the second transistor element and a hard mask covering the first transistor element. A pair of cavities is formed adjacent the gate electrode of the second transistor element. A pair of stress-creating elements is formed in the cavities and the hard mask is at least partially removed.

    摘要翻译： 形成半导体结构的方法包括提供包括第一晶体管元件和第二晶体管元件的半导体衬底。 第一晶体管元件和第二晶体管元件中的每一个包括栅电极。 在第一晶体管元件和第二晶体管元件上沉积应力材料层。 被施加的材料层被加工成从与第二晶体管元件的栅电极相邻的应力材料层侧壁间隔和覆盖第一晶体管元件的硬掩模形成。 在第二晶体管元件的栅电极附近形成一对空腔。 在空腔中形成一对应力产生元件，并且至少部分地去除硬掩模。

    Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process
    95.
    发明授权
    Methods of making transistor devices with elevated source/drain regions to accommodate consumption during metal silicide formation process 有权
    制造具有升高的源极/漏极区域的晶体管器件以适应金属硅化物形成过程中的消耗的方法

    公开(公告)号：US09490344B2

    公开(公告)日：2016-11-08

    申请号：US13345922

    申请日：2012-01-09

    申请人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    发明人： Stefan Flachowsky ,  Jan Hoentschel ,  Thilo Scheiper

    IPC分类号： H01L21/02 ,  H01L21/334 ,  H01L21/336 ,  H01L29/66 ,  H01L29/78

    CPC分类号： H01L29/66628 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7847 ,  H01L29/7848

    摘要： Disclosed herein are various semiconductor devices with dual metal silicide regions and to various methods of making such devices. One illustrative method disclosed herein includes the steps of forming an upper portion of a source/drain region that is positioned above a surface of a semiconducting substrate, wherein the upper portion of the source/drain region has an upper surface that is positioned above the surface of the substrate by a distance that is at least equal to a target thickness of a metal silicide region to be formed in the upper portion of the source/drain region and forming the metal silicide region in the upper portion of the source/drain region.

    摘要翻译： 本文公开了具有双金属硅化物区域的各种半导体器件以及制造这种器件的各种方法。 本文公开的一种说明性方法包括以下步骤：形成位于半导体衬底的表面上方的源极/漏极区的上部，其中源极/漏极区的上部具有位于表面上方的上表面 以至少等于待形成在源/漏区上部的金属硅化物区域的目标厚度的距离，并在源/漏区的上部形成金属硅化物区域。

    Multiple gate transistor having homogenously silicided fin end portions
    96.
    发明授权
    Multiple gate transistor having homogenously silicided fin end portions 有权
    具有均匀硅化鳍片端部的多栅极晶体管

    公开(公告)号：US08791509B2

    公开(公告)日：2014-07-29

    申请号：US12620083

    申请日：2009-11-17

    申请人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    发明人： Sven Beyer ,  Patrick Press ,  Rainer Giedigkeit ,  Jan Hoentschel

    IPC分类号： H01L29/786 ,  H01L29/78 ,  H01L29/772

    CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795

    摘要： In a multiple gate transistor, the plurality of Fins of the drain or source of the transistor are electrically connected to each other by means of a common contact element, wherein enhanced uniformity of the corresponding contact regions may be accomplished by an enhanced silicidation process sequence. For this purpose, the Fins may be embedded into a dielectric material in which an appropriate contact opening may be formed to expose end faces of the Fins, which may then act as silicidation surface areas.

    摘要翻译： 在多栅极晶体管中，晶体管的漏极或源极的多个鳍状物通过公共接触元件彼此电连接，其中相应的接触区域的增强的均匀性可以通过增强的硅化工艺序列来实现。 为此，金箔可以嵌入电介质材料中，其中可以形成适当的接触开口以露出金属丝的端面，其然后可以作为硅化表面区域。

    Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers
    100.
    发明申请
    Methods of Forming Semiconductor Devices with Embedded Semiconductor Material as Source/Drain Regions Using a Reduced Number of Spacers 有权
    用嵌入式半导体材料形成半导体器件作为源/漏区域的方法使用减少的间隔数

    公开(公告)号：US20130302956A1

    公开(公告)日：2013-11-14

    申请号：US13470454

    申请日：2012-05-14

    申请人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

    发明人： Stefan Flachowsky ,  Ricardo P. Mikalo ,  Jan Hoentschel

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/26513 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7834

    摘要： In one example, a method disclosed herein includes the steps of forming a gate structure for a first transistor and a second transistor above a semiconducting substrate, forming a liner layer above the gate structures and performing a plurality of extension ion implant processes through the liner layer to form extension implant regions in the substrate for the first transistor and the second transistor. The method further includes forming a first sidewall spacer proximate the gate structure for the first transistor and a patterned hard mask layer positioned above the second transistor, performing at least one etching process to remove the first sidewall spacer, the patterned hard mask layer and the liner layer, forming a second sidewall spacer proximate both of the gate structures and performing a plurality of source/drain ion implant processes to form deep source/drain implant regions in the substrate for the first transistor and the second transistor.

    摘要翻译： 在一个示例中，本文公开的方法包括以下步骤：在半导体衬底上形成用于第一晶体管和第二晶体管的栅极结构，在栅极结构上方形成衬底层，并通过衬底层执行多个延伸离子注入工艺 以在第一晶体管和第二晶体管的衬底中形成延伸注入区。 该方法还包括形成靠近第一晶体管的栅极结构的第一侧壁隔离物和位于第二晶体管上方的图案化硬掩模层，执行至少一个蚀刻工艺以去除第一侧壁间隔物，图案化硬掩模层和衬垫 形成靠近两个栅极结构的第二侧壁间隔件，并且执行多个源极/漏极离子注入工艺以在用于第一晶体管和第二晶体管的衬底中形成深源极/漏极注入区域。