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    Tristate structures for programmable logic devices
    91.
    发明授权
    Tristate structures for programmable logic devices 失效
    可编程逻辑器件的三态结构

    公开(公告)号：US06882177B1

    公开(公告)日：2005-04-19

    申请号：US09832685

    申请日：2001-04-10

    申请人： Srinivas Reddy ,  Richard G. Cliff

    发明人： Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： H03K19/177 ,  G06F7/38

    CPC分类号： H03K19/17752 ,  H03K19/17728 ,  H03K19/17736

    摘要： A programmable logic device architecture including tristate structures. The programmable logic device architecture provides tristate structures which may be logically or programmably controlled, or both. Through these tristate structures, the logic elements may be coupled to the programmable interconnect, where they may be coupled with other logic elements of the programmable logic device. Using these tristate structures, the signal pathways of the architecture may be dynamically reconfigured.

    摘要翻译： 包括三态结构的可编程逻辑器件架构。 可编程逻辑器件架构提供了可逻辑地或可编程地控制的三态结构，或两者。 通过这些三态结构，逻辑元件可以耦合到可编程互连，其中它们可以与可编程逻辑器件的其它逻辑元件耦合。 使用这些三态结构，可以动态地重新配置架构的信号路径。

    Phase-locked loop circuitry for programmable logic devices
    92.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06469553B1

    公开(公告)日：2002-10-22

    申请号：US09811946

    申请日：2001-03-19

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L700

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    Programmable logic device with hierarchical interconnection resources
    93.
    发明授权
    Programmable logic device with hierarchical interconnection resources 有权
    具有分层互连资源的可编程逻辑器件

    公开(公告)号：US06417694B1

    公开(公告)日：2002-07-09

    申请号：US09956748

    申请日：2001-09-19

    申请人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    发明人： Srinivas T. Reddy ,  Richard G. Cliff ,  Christopher F. Lane ,  Ketan H. Zaveri ,  Manuel M. Mejia ,  David Jefferson ,  Bruce B. Pedersen ,  Andy L. Lee

    IPC分类号： H03K19177

    CPC分类号： H03K19/17736 ,  H03K19/17704 ,  H03K19/17728

    摘要： A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e.g., for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

    摘要翻译： 可编程逻辑器件具有多个可编程逻辑超区域，该多个可编程逻辑超区域以相邻的行和列的超区域的二维阵列布置在器件上。 水平和垂直超超导区域互连导体分别与每行和列相关联。 每个超区域包括多个可编程逻辑区域，并且每个区域包括多个可编程逻辑子区域。 区域间互连导体与每个超区域相关联，主要用于将信号引入超区域并互连超区域中的区域。 本地导体与每个区域相关联，主要用于使信号进入该区域。 在超区域级别，设备可以是水平和垂直同构的，这有助于产生具有一个或几乎一个的低纵横比的设备。 可以提供共享的驱动器电路（例如，用于（1）从子区域和水平和/或垂直导体接收信号，以及（2）将选择的接收信号施加到区域间导体，水平和垂直导体，以及可能的 也是当地的导体）。 水平和/或垂直导体可以轴向分割，并且可以提供缓冲电路用于将可编程地拼接在一起的轴向段以制造更长的导体。

    Phase-locked loop circuitry for programmable logic devices
    96.
    发明授权
    Phase-locked loop circuitry for programmable logic devices 有权
    用于可编程逻辑器件的锁相环电路

    公开(公告)号：US06218876B1

    公开(公告)日：2001-04-17

    申请号：US09392095

    申请日：1999-09-08

    申请人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    发明人： Chiakang Sung ,  Robert R. N. Bielby ,  Richard G. Cliff ,  Edward Aung

    IPC分类号： H03L706

    CPC分类号： H03K19/1774 ,  G06F1/04 ,  G06F1/08 ,  H03K19/17732 ,  H03L7/0891 ,  H03L7/23

    摘要： A programmable logic device is provided with phase-locked loop (“PLL”) circuitry that includes two serially connected PLL circuits. An input clock signal is processed by a first of the PLL circuits to produce an intermediate clock signal having a frequency different from the input clock signal frequency. The intermediate clock signal is processed by the second PLL circuit to produce a final modified clock signal having a frequency different from both the input clock signal frequency and the intermediate clock signal frequency. By providing two serially connected PLL circuits, each PLL circuit can be required to operate with frequencies in a narrower range than might otherwise be required in a single PLL circuit required to produce a given input-to-final frequency change. Other circuitry on the programmable logic device (e.g., input/output registers and programmable logic circuitry for processing data signals) is responsive to the input and final modified clock signals. The two PLL circuits may alternatively be used separately or partly separately.

    摘要翻译： 可编程逻辑器件提供有锁相环（“PLL”）电路，其包括两个串联的PLL电路。 输入时钟信号由第一PLL电路处理以产生具有与输入时钟信号频率不同的频率的中间时钟信号。 中间时钟信号由第二PLL电路处理以产生具有与输入时钟信号频率和中间时钟信号频率两者不同的频率的最终修改的时钟信号。 通过提供两个串联连接的PLL电路，可以要求每个PLL电路以比在产生给定的输入到最终频率变化所需的单个PLL电路中可能需要的更窄的范围内工作。 可编程逻辑器件上的其他电路（例如，用于处理数据信号的输入/输出寄存器和可编程逻辑电路）响应于输入和最终修改的时钟信号。 两个PLL电路可以单独使用或部分单独使用。

    System for distributing clocks using a delay lock loop in a programmable logic circuit
    98.
    发明授权
    System for distributing clocks using a delay lock loop in a programmable logic circuit 失效
    用于在可编程逻辑电路中使用延迟锁定环路分配时钟的系统

    公开(公告)号：US5963069A

    公开(公告)日：1999-10-05

    申请号：US971315

    申请日：1997-11-17

    申请人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    发明人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： G06F1/10 ,  H03K19/177 ,  H03L7/081 ,  H03L7/087 ,  H03L7/08

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    摘要： A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

    摘要翻译： 一种用于将时钟信号分配给集成电路上的许多点的系统（100）。 该系统包括使用具有特定数字电路的延迟锁定环来完成相位误差检测和延迟元件选择。 在一个实施例中，使用两个触发器来检测相位误差。 在另一个实施例中，使用宏（202）和微相位检测器（218），并且通过使用第一级中的移位寄存器（210）和在第二级中的计数器（220），两级执行延迟元件选择 。 本发明的另一个特征是将参考时钟或同步时钟分配到集成电路上的电路的不同部分的能力。 提供可选择的多个时钟分配系统。

    Look up table implementation of fast carry arithmetic and exclusive-OR operations
    99.
    发明授权
    Look up table implementation of fast carry arithmetic and exclusive-OR operations 失效
    查找表执行快速进位算术和异或运算

    公开(公告)号：US5481486A

    公开(公告)日：1996-01-02

    申请号：US166300

    申请日：1993-12-13

    申请人： Richard G. Cliff ,  L. Todd Cope

    发明人： Richard G. Cliff ,  L. Todd Cope

    IPC分类号： G06F7/00 ,  G06F1/035 ,  G06F7/50 ,  G06F7/501 ,  G06F7/575 ,  H03K19/177 ,  H03K21/00 ,  H03K23/00

    CPC分类号： G06F7/501 ,  G06F1/0356 ,  G06F7/575 ,  H03K19/17704 ,  H03K19/17728 ,  H03K21/00

    摘要： Look up tables for use in programmable logic devices are modified to facilitate use of those tables to provide adders (including subtracters) and various types of counters. Each look up table is effectively partitioned into smaller look up tables when an adder or counter is required. One portion of the partitioned table is used to provide a sum out signal, while the other portion of the partitioned table is used to provide a fast carry out signal for application to the next stage of the adder or counter. If desired, each logic module including such a look up table may further include logic circuitry for logically combining its normal output with the signal applied to its carry in input to facilitate the provision of wide fan in functions having more inputs than can be accepted by a single logic module.

    摘要翻译： 修改用于可编程逻辑器件的查找表以便于使用这些表来提供加法器（包括减法器）和各种类型的计数器。 当需要加法器或计数器时，每个查找表有效地分割成更小的查找表。 分割表的一部分用于提供和出信号，而分割表的另一部分用于提供快速进位信号以供应用于加法器或计数器的下一级。 如果需要，包括这种查找表的每个逻辑模块还可以包括逻辑电路，用于逻辑地将其正常输出与施加到其进位输入中的信号进行逻辑组合，以便于提供具有比可被 单逻辑模块。