Method for controlling voiding and bridging in silicide formation
    91.
    发明授权
    Method for controlling voiding and bridging in silicide formation 有权
    控制硅化物形成中孔隙和桥接的方法

    公开(公告)号:US07129169B2

    公开(公告)日:2006-10-31

    申请号:US10709534

    申请日:2004-05-12

    IPC分类号: H01L21/44 H01L21/3205

    摘要: A method for forming a metal silicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

    摘要翻译: 一种用于形成用于半导体器件的金属硅化物接触的方法包括在衬底上形成难熔金属层,该衬底包括所述衬底的有源区和非有源区,并在难熔金属层上形成覆盖层。 反面拉伸层形成在覆盖层上方,其中相对抗拉层选自材料,使得在相对拉伸层和盖层之间产生相对的方向应力,相对于难熔金属之间产生的方向应力 层和盖层。

    METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION
    94.
    发明申请
    METHOD FOR CONTROLLING VOIDING AND BRIDGING IN SILICIDE FORMATION 有权
    用于控制硅化物形成中的阻塞和桥接的方法

    公开(公告)号:US20050255699A1

    公开(公告)日:2005-11-17

    申请号:US10709534

    申请日:2004-05-12

    摘要: A method for forming a metal suicide contact for a semiconductor device includes forming a refractory metal layer over a substrate, including active and non-active area of said substrate, and forming a cap layer over the refractory metal layer. A counter tensile layer is formed over the cap layer, wherein the counter tensile layer is selected from a material such that an opposing directional stress is created between the counter tensile layer and the cap layer, with respect to a directional stress created between the refractory metal layer and the cap layer.

    摘要翻译: 用于形成用于半导体器件的金属硅化物接触的方法包括在包括所述衬底的有源和非有源区域的衬底上形成难熔金属层,并在难熔金属层上形成覆盖层。 反面拉伸层形成在覆盖层上方,其中相对抗拉层选自材料,使得在相对拉伸层和盖层之间产生相对的方向应力,相对于难熔金属之间产生的方向应力 层和盖层。

    Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi
    96.
    发明授权
    Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi 失效
    CoSi的预退火,以防止在Ti-O-N和CoSi之间形成非晶层

    公开(公告)号:US06878624B1

    公开(公告)日:2005-04-12

    申请号:US10674645

    申请日:2003-09-30

    摘要: The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

    摘要翻译: 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构,以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构,其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物,并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散,使形成的无定形Ti钴硅化物层最小化。 因此,非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

    PRE-ANNEAL OF COSI, TO PREVENT FORMATION OF AMORPHOUS LAYER BETWEEN TI-O-N AND COSI
    97.
    发明申请
    PRE-ANNEAL OF COSI, TO PREVENT FORMATION OF AMORPHOUS LAYER BETWEEN TI-O-N AND COSI 失效
    COSE预先预防TI-O-N和COSI之间形成非晶层

    公开(公告)号:US20050070098A1

    公开(公告)日:2005-03-31

    申请号:US10674645

    申请日:2003-09-30

    摘要: The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

    摘要翻译: 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构,以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构,其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物,并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散,使形成的无定形Ti钴硅化物层最小化。 因此,非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed
    100.
    发明授权
    Method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure and structure formed 有权
    在半导体结构中的金属硅化物层的顶部上形成TiN层的方法和形成的结构

    公开(公告)号:US06436823B1

    公开(公告)日:2002-08-20

    申请号:US09679738

    申请日:2000-10-05

    IPC分类号: H01L2144

    摘要: A method for forming a TiN layer on top of a metal silicide layer in a semiconductor structure without the formation of a thick amorphous layer containing Ti, Co and Si and the structure formed are provided. In the method, after a Ti layer is deposited on top of a metal silidide layer, a dual-step annealing process is conducted in which a low temperature annealing in a forming gas (or ammonia) at a temperature not higher than 500° C. is first conducted for less than 2 hours followed by a high temperature annealing in a nitrogen-containing gas (or ammonia) at a second temperature not lower than 500° for less than 2 hours to form the TiN layer. The present invention method prevents the problem usually caused by a thick amorphous material layer of Ti—Si—Co which produces weakly bonded Ti which reacts with fluorine atoms from WF6 during a subsequent CVD W deposition process and causes liner failure due to a volume expansion of the amorphous material. The maximum thickness of the amorphous material layer formed by the present invention method is less than 5 nm which minimizes the line failure problem.

    摘要翻译: 提供了一种在半导体结构中的金属硅化物层的顶部上形成TiN层的方法,而不形成含有Ti,Co和Si的厚非晶层以及形成的结构。 在该方法中,在金属硅化物层的顶部沉积Ti层之后,进行双相退火工艺,其中在不高于500℃的温度下在成形气体(或氨)中进行低温退火。 首先进行少于2小时,然后在不低于500℃的第二温度下在含氮气体(或氨)中进行低温退火2小时以形成TiN层。 本发明的方法防止了在随后的CVD W沉积过程中由Ti-Si-Co的厚的无定形材料层产生的弱结合的Ti与来自WF6的氟原子反应而产生的弱结合的问题,并导致由于体积膨胀引起的衬管故障 无定形材料。 通过本发明方法形成的非晶材料层的最大厚度小于5nm,这使线路故障问题最小化。