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    Back-End-of-Line Resistive Semiconductor Structures
    91.
    发明申请
    Back-End-of-Line Resistive Semiconductor Structures 有权
    后端电阻半导体结构

    公开(公告)号：US20100038754A1

    公开(公告)日：2010-02-18

    申请号：US12191683

    申请日：2008-08-14

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Robert Robison ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L27/115 ,  H01L23/5256 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In one embodiment, a back-end-of-line (BEOL) resistive structure comprises a second metal line embedded in a second dielectric layer and overlying a first metal line embedded in a first dielectric layer. A doped semiconductor spacer or plug laterally abutting sidewalls of the second metal line and vertically abutting a top surface of the first metal line provides a resistive link between the first and second metal lines. In another embodiment, another BEOL resistive structure comprises a first metal line and a second metal line are embedded in a dielectric layer. A doped semiconductor spacer or plug laterally abutting the sidewalls of the first and second metal lines provides a resistive link between the first and second metal lines.

    摘要翻译： 在一个实施例中，后端行（BEOL）电阻结构包括嵌入在第二电介质层中的第二金属线，并且覆盖嵌入在第一介电层中的第一金属线。 横向邻接第二金属线的侧壁并垂直邻接第一金属线的顶表面的掺杂半导体间隔物或插塞提供第一和第二金属线之间的电阻连接。 在另一个实施例中，另一个BEOL电阻结构包括第一金属线，第二金属线嵌入电介质层。 横向邻接第一和第二金属线的侧壁的掺杂半导体间隔件或插塞提供第一和第二金属线之间的电阻连接。

    Patterned silicon-on-insulator layers and methods for forming the same
    92.
    发明授权
    Patterned silicon-on-insulator layers and methods for forming the same 有权
    图案化的绝缘体上硅层及其形成方法

    公开(公告)号：US07659599B2

    公开(公告)日：2010-02-09

    申请号：US12049258

    申请日：2008-03-14

    申请人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Roger Allen Booth, Jr. ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76243

    摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

    摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof
    94.
    发明授权
    Electrically programmable fuse structures with terminal portions residing at different heights, and methods of fabrication thereof 失效
    具有位于不同高度的端子部分的电可编程熔丝结构及其制造方法

    公开(公告)号：US07645645B2

    公开(公告)日：2010-01-12

    申请号：US11372334

    申请日：2006-03-09

    申请人： William P. Hovis ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    发明人： William P. Hovis ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： H01L21/82

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside at different heights relative to a supporting surface of the fuse structure, and the interconnecting fuse element transitions between the different heights of the first terminal portion and the second terminal portion. The first and second terminal portions are oriented parallel to the supporting surface, while the fuse element includes a portion oriented orthogonal to the supporting surface, and includes at least one right angle bend where transitioning from at least one of the first and second terminal portions to the orthogonal oriented portion of the fuse element.

    摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分相对于熔丝结构的支撑表面驻留在不同的高度处，并且互连熔丝元件在第一端子部分和第二端子部分的不同高度之间转变。 第一端子部分和第二端子部分平行于支撑表面定向，而熔丝元件包括垂直于支撑表面定向的部分，并且包括至少一个直角弯曲部，其从第一和第二端子部分中的至少一个过渡到 保险丝元件的正交取向部分。

    METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY
    95.
    发明申请
    METHODS OF FABRICATING A DEVICE STRUCTURE FOR USE AS A MEMORY CELL IN A NON-VOLATILE RANDOM ACCESS MEMORY 失效
    在非易失性随机存取存储器中用作存储器单元的器件结构的制作方法

    公开(公告)号：US20090280607A1

    公开(公告)日：2009-11-12

    申请号：US12117950

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L27/1203 ,  H01L29/66825

    摘要： Methods for fabricating a device structure for use as a memory cell in a non-volatile random access memory. The method includes forming first and second semiconductor bodies on the insulating layer that have a separated, juxtaposed relationship, doping the first semiconductor body to form a source and a drain, and partially removing the second semiconductor body to define a floating gate electrode adjacent to the channel of the first semiconductor body. The method further includes forming a first dielectric layer between the channel of the first semiconductor body and the floating gate electrode, forming a second dielectric layer on a top surface of the floating gate electrode, and forming a control gate electrode on the second dielectric layer that cooperates with the floating gate electrode to control carrier flow in the channel in the first semiconductor body.

    摘要翻译： 制造用作非易失性随机存取存储器中的存储单元的器件结构的方法。 该方法包括在绝缘层上形成具有分开且并置的关系的第一和第二半导体本体，掺杂第一半导体本体以形成源极和漏极，以及部分地移除第二半导体本体以限定邻近 第一半导体体的通道。 该方法还包括在第一半导体本体的沟道与浮栅之间形成第一电介质层，在浮置栅电极的顶表面上形成第二电介质层，在第二电介质层上形成控制栅电极， 与浮栅电极配合，以控制第一半导体体的沟道中的载流子流动。

    DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY
    96.
    发明申请
    DEVICE STRUCTURES FOR A MEMORY CELL OF A NON-VOLATILE RANDOM ACCESS MEMORY AND DESIGN STRUCTURES FOR A NON-VOLATILE RANDOM ACCESS MEMORY 失效
    非易失性随机访问存储器的存储单元的设备结构和非易失性随机存取存储器的设计结构

    公开(公告)号：US20090278185A1

    公开(公告)日：2009-11-12

    申请号：US12118241

    申请日：2008-05-09

    申请人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Kiran V. Chatty ,  Robert J. Gauthier, JR. ,  Jed H. Rankin ,  Yun Shi ,  William R. Tonti

    IPC分类号： H01L29/00 ,  G06F9/455

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L29/42324

    摘要： Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.

    摘要翻译： 非易失性随机存取存储器（NVRAM）中存储单元的器件和设计结构。 器件结构包括与绝缘层直接接触的半导体本体，控制栅电极和与绝缘层直接接触的浮栅电极。 半导体本体包括源极，漏极以及源极和漏极之间的沟道。 浮置栅电极与半导体本体的沟道并置并且设置在控制栅电极和绝缘层之间。 第一电介质层设置在半导体本体的沟道和浮栅之间。 第二介电层设置在控制栅电极和浮栅电极之间。

    CMOS devices adapted to prevent latchup and methods of manufacturing the same
    97.
    发明授权
    CMOS devices adapted to prevent latchup and methods of manufacturing the same 失效
    适于防止闭锁的CMOS器件及其制造方法

    公开(公告)号：US07615828B2

    公开(公告)日：2009-11-10

    申请号：US11456357

    申请日：2006-07-10

    申请人： Jack A. Mandelman ,  William R. Tonti

    发明人： Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/7833 ,  H01L21/743 ,  H01L21/823814 ,  H01L21/823878 ,  H01L27/0921 ,  H01L29/665 ,  H01L2027/1189

    摘要： In a first aspect, a first apparatus is provided. The first apparatus is a semiconductor device on a substrate that includes (1) a first metal-oxide-semiconductor field-effect transistor (MOSFET); (2) a second MOSFET coupled to the first MOSFET, wherein portions of the first and second MOSFETs form first and second bipolar junction transistors (BJTs) which are coupled into a loop; and (3) a conductive region that electrically couples a source diffusion region of the first or second MOSFET with a doped well region below the source diffusion region. The conductive region is adapted to prevent an induced current from forming in the loop. Numerous other aspects are provided.

    摘要翻译： 在第一方面中，提供了一种第一装置。 第一装置是衬底上的半导体器件，其包括：（1）第一金属氧化物半导体场效应晶体管（MOSFET）; （2）耦合到所述第一MOSFET的第二MOSFET，其中所述第一和第二MOSFET的部分形成耦合到环路中的第一和第二双极结型晶体管（BJT）; 和（3）将第一或第二MOSFET的源极扩散区域与源极扩散区域下方的掺杂阱区域电耦合的导电区域。 导电区域适于防止在环路中形成感应电流。 提供了许多其他方面。

    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD
    99.
    发明申请
    ANTI-FUSE DEVICE STRUCTURE AND ELECTROPLATING CIRCUIT STRUCTURE AND METHOD 有权
    抗保护器件结构和电镀电路结构与方法

    公开(公告)号：US20090206447A1

    公开(公告)日：2009-08-20

    申请号：US12031761

    申请日：2008-02-15

    申请人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    发明人： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  William R. Tonti

    IPC分类号： H01L23/525 ,  H01L21/44

    CPC分类号： H01L23/5252 ,  C25D5/02 ,  C25D5/10 ,  C25D21/12 ,  H01L21/2885 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Disclosed are embodiments of a circuit and method for electroplating a feature (e.g., a BEOL anti-fuse device) onto a wafer. The embodiments eliminate the use of a seed layer and, thereby, minimize subsequent processing steps (e.g., etching or chemical mechanical polishing (CMP)). Specifically, the embodiments allow for selective electroplating metal or alloy materials onto an exposed portion of a metal layer in a trench on the front side of a substrate. This is accomplished by providing a unique wafer structure that allows a current path to be established from a power supply through a back side contact and in-substrate electrical connector to the metal layer. During electrodeposition, current flow through the current path can be selectively controlled. Additionally, if the electroplated feature is an anti-fuse device, current flow through this current path can also be selectively controlled in order to program the anti-fuse device.

    摘要翻译： 公开了用于将特征（例如，BEOL反熔丝器件）电镀到晶片上的电路和方法的实施例。 这些实施例消除了种子层的使用，从而使随后的处理步骤（例如，蚀刻或化学机械抛光（CMP））最小化。 具体地，实施例允许将金属或合金材料选择性地电镀到衬底前侧的沟槽中的金属层的暴露部分上。 这是通过提供一种独特的晶片结构来实现的，该晶片结构允许从电源通过后侧接触和衬底上的电连接器建立到金属层的电流路径。 在电沉积期间，可以选择性地控制通过电流路径的电流。 此外，如果电镀特征是反熔丝器件，则也可以选择性地控制通过该电流路径的电流，以便编程反熔丝器件。

    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP
    100.
    发明申请
    SEMICONDUCTOR STRUCTURE AND SYSTEM FOR FABRICATING AN INTEGRATED CIRCUIT CHIP 有权
    用于制造集成电路芯片的半导体结构和系统

    公开(公告)号：US20090134463A1

    公开(公告)日：2009-05-28

    申请号：US12348344

    申请日：2009-01-05

    申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, JR. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

    IPC分类号： H01L29/78

    CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

    摘要： A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

    摘要翻译： 一种半导体结构和用于制造集成电路芯片的系统。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。 用于制造集成电路芯片的系统能够：提供与半导体晶片直接机械接触的掩埋氧化物层; 并且在掩埋氧化物层上同时形成至少一个鳍式场效应晶体管和至少一个厚体器件。