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    LOW POWER HIGH-SPEED OUTPUT DRIVER
    91.
    发明申请
    LOW POWER HIGH-SPEED OUTPUT DRIVER 有权
    低功率高速输出驱动器

    公开(公告)号：US20090230993A1

    公开(公告)日：2009-09-17

    申请号：US12049701

    申请日：2008-03-17

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03K19/0175 ,  H03K3/00

    CPC classification number: H03K19/017509

    Abstract: Low power high-speed output driver. An array of switches (some of which are inverting switches whose connectivity is governed oppositely as the control signal provided to it) is implemented such that an input signal governs the connectivity of those switches. A resistor is coupled between the nodes interposed between the switches of the array, and an output signal is taken from the nodes at ends of the resistor. The high voltage level of such an output driver is truly the level of the power supply energizing the circuit (e.g., VDD) while still consuming relatively low power.

    Abstract translation: 低功耗高速输出驱动。 一组开关（其中一些是反向开关，其连接性与提供给它的控制信号相反地控制），使得输入信号控制这些开关的连接。 电阻器耦合在插入阵列的开关之间的节点之间，并且从电阻器端部处的节点获取输出信号。 这种输出驱动器的高电压电平实际上是在仍然消耗相对较低的功率的情况下为电路供电（例如，VDD）的电源的电平。

    Phase control for interleaved analog-to-digital conversion for electronic dispersion compensation
    92.
    发明授权
    Phase control for interleaved analog-to-digital conversion for electronic dispersion compensation 失效
    用于电子色散补偿的交错模数转换的相位控制

    公开(公告)号：US07525470B2

    公开(公告)日：2009-04-28

    申请号：US11845765

    申请日：2007-08-27

    Applicant: Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

    Inventor： Vasudevan Parthasarthy ,  Sudeep Bhoja ,  Vivek Telang ,  Afshin Momtaz

    IPC: H03M1/12

    CPC classification number: H03M1/0836 ,  H03M1/1215 ,  H03M1/183

    Abstract: Embodiments include a system for performing dispersion compensation on an electromagnetic signal received over a communication channel, the electromagnetic signal bearing information at a symbol rate. An interleaved analog to digital converter (“ADC”) block may be used, wherein the interleaved ADC block may be configured to generate a plurality of digitally sampled signals from the electromagnetic signal. An interleaved equalizer block may be configured to digitally process each of the digitally sampled signals generated by the ADC block to generate a plurality of digitally equalized signals. A multiplexer may be configured to aggregate the digitally equalized signals into a composite output signal.

    Abstract translation: 实施例包括一种用于对通过通信信道接收的电磁信号进行色散补偿的系统，该电磁信号以符号速率承载信息。 可以使用交错模数转换器（“ADC”）块，其中交织的ADC块可以被配置为从电磁信号生成多个数字采样的信号。 交织的均衡器块可以被配置为数字地处理由ADC块产生的数字采样信号中的每一个以产生多个数字均衡的信号。 多路复用器可以被配置为将数字均衡的信号聚合成复合输出信号。

    Multiple channel synchronized clock generation scheme
    93.
    发明申请
    Multiple channel synchronized clock generation scheme 有权
    多通道同步时钟生成方案

    公开(公告)号：US20080152062A1

    公开(公告)日：2008-06-26

    申请号：US11705316

    申请日：2007-02-12

    Applicant: Namik K. Kocaman ,  Afshin Momtaz

    Inventor： Namik K. Kocaman ,  Afshin Momtaz

    IPC: H04L7/02

    CPC classification number: H04L7/033 ,  H04L7/0008

    Abstract: Multiple channel synchronized clock generation scheme. A novel approach is presented herein in which synchronized clock signals are generated that can be used in parallel processing of deserialized signals. When a serial input signal is received, it can be deserialized into a plurality of parallel signals, and each of these parallel signals can be processed at a frequency that is lower than the frequency of the serial signal. Overall, the frequency at which all of the parallel signals are processed can be the same or substantially close to the frequency of the serial signal, so that throughput within a communication system is not compromised or undesirably reduced. This novel approach is operable to perform independent adjustment of the operational parameters within an apparatus that is operable to perform multiple channel synchronized clock generation (e.g., phase rotation and/or division of signals within each of the individual channels can be adjusted independently).

    Abstract translation: 多通道同步时钟生成方案。 本文提出了一种新颖的方法，其中产生可以并行处理反序列化信号的同步时钟信号。 当串行输入信号被接收时，它可以被反序列化成多个并行信号，并且这些并行信号中的每一个可以以低于串行信号频率的频率进行处理。 总的来说，所有并行信号被处理的频率可以相同或基本上接近串行信号的频率，使得通信系统内的吞吐量不会受到损害或不期望地减少。 这种新颖的方法可操作以对可操作以执行多信道同步时钟生成的装置中的操作参数进行独立调整（例如，可以独立地调整各个信道内的信号的相位旋转和/或除法）。

    Method and apparatus for high speed signal recovery
    94.
    发明授权
    Method and apparatus for high speed signal recovery 失效
    用于高速信号恢复的方法和装置

    公开(公告)号：US07386085B2

    公开(公告)日：2008-06-10

    申请号：US10159788

    申请日：2002-05-30

    Applicant: Afshin Momtaz ,  Kambiz Vakilian

    Inventor： Afshin Momtaz ,  Kambiz Vakilian

    IPC: H04L7/033

    CPC classification number: H03L7/081 ,  H03L7/0891 ,  H03L7/093 ,  H04L7/033

    Abstract: A closed-loop circuitry includes, in part, a loop filter and a current source/sink coupled to the loop filter to adjust the phase/frequency of the signal generated by the closed-loop circuitry. Because the voltage generated by the loop filter has a relatively low frequency, the current source/sink is operable at a relatively low frequency. Each current source and current sink may be a current digital-to-analog (DAC). The amount of current sourced into or sunk out of the loop filter by the current DAC is varied by setting the associated bits of a multi-bit signal. If the closed-loop circuitry is differential, a current source is coupled to the loop filter adapted to receive the differentially high signal, and a current source is coupled to the loop filter adapted to receive the differentially low signal.

    Abstract translation: 闭环电路部分地包括环路滤波器和耦合到环路滤波器的电流源/宿，以调整由闭环电路产生的信号的相位/频率。 由于环路滤波器产生的电压具有相对低的频率，所以电流源/汇可以相对较低的频率工作。 每个电流源和电流吸收器可以是当前的数模（DAC）。 通过设置当前DAC的环路滤波器中的电流或者从环路滤波器中吸出的电流量可通过设置多位信号的相关位来改变。 如果闭环电路是差分的，则电流源耦合到适于接收差分高信号的环路滤波器，并且电流源耦合到适于接收差分低信号的环路滤波器。

    Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer
    96.
    发明授权
    Using clock and data recovery phase adjust to set loop delay of a decision feedback equalizer 失效
    使用时钟和数据恢复阶段调整设置决策反馈均衡器的回路延迟

    公开(公告)号：US07330508B2

    公开(公告)日：2008-02-12

    申请号：US10774725

    申请日：2004-02-09

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03L7/30 ,  H03K5/159 ,  H03D3/24

    CPC classification number: H04L25/03057 ,  H03L7/081 ,  H04B10/2507 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349 ,  H04L2025/03579

    Abstract: In a method and apparatus for communicating data, a decision feedback equalizer equalizes received data to reduce channel related distortion in the received data. An extracted clock signal is generated from the equalized data. The phase of the extracted clock signal may be adjusted to compensate for processing delay during equalization of the received data. The extracted clock signal may be used to clock a retimer of the decision feedback equalizer to generate recovered data.

    Abstract translation: 在用于传送数据的方法和装置中，判决反馈均衡器对接收到的数据进行均衡以减少接收到的数据中的信道相关失真。 从均衡数据生成提取的时钟信号。 提取的时钟信号的相位可以被调整以补偿在接收的数据的均衡期间的处理延迟。 提取的时钟信号可以用于对判决反馈均衡器的重定时器进行时钟以产生恢复的数据。

    Automatic gain control with three states of operation
    98.
    发明授权
    Automatic gain control with three states of operation 有权
    具有三种运行状态的自动增益控制

    公开(公告)号：US07205841B2

    公开(公告)日：2007-04-17

    申请号：US11112041

    申请日：2005-04-22

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03F3/45973 ,  H03F2200/435 ,  H03F2200/78 ,  H03G3/001 ,  H03G3/30

    Abstract: A method and apparatus for an automatic gain control (AGC) loop that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA.

    Abstract translation: 一种利用冷冻和解​​冻状态的自动增益控制（AGC）回路的方法和装置。 基于监视时间窗口的VGA增益控制代码的净变化，冻结过程将AGC从NORMAL状态移动到TRANSITION状态。 基于监视时间窗口的VGA增益控制代码的净变化，冷冻过程然后将AGC从TRANSITION状态移动到FROZEN状态。 基于VGA输出端的信号幅度变化，解冻过程将AGC从FROZEN状态移动到NORMAL状态。

    Phase lock loop with cycle drop and add circuitry
    99.
    发明授权
    Phase lock loop with cycle drop and add circuitry 有权
    锁相环，循环下降和加电路

    公开(公告)号：US07088797B2

    公开(公告)日：2006-08-08

    申请号：US10241140

    申请日：2002-09-10

    Applicant: Afshin Momtaz ,  David Kyong-Sik Chung ,  Pang-Cheng Hsu

    Inventor： Afshin Momtaz ,  David Kyong-Sik Chung ,  Pang-Cheng Hsu

    IPC: H03D3/24 ,  H03L7/06

    CPC classification number: H04J3/076 ,  H03L7/0891 ,  H03L7/183

    Abstract: Phase locked loops that can adjust the frequency of a clock signal are provided. A transmitter adjusts its data transmission rate in response to the clock signal to accommodate different data transmission protocols. A phase locked loop can add or drop cycles from an input clock signal in response to one or more signals from a receiver. The signals from the receiver indicate the transmission rate of the incoming data signal. The phase locked loop can drop cycles from the clock signal to decrease the frequency of the clock signal. The transmitter then decreases its data transmission rate in response to the reduced frequency of the clock signal. The phase locked loop can also add cycles to the clock signal to increase the frequency of the clock signal. The transmitter increases its data transmission rate in response to the increased frequency of the clock signal.

    Abstract translation: 提供了可调节时钟信号频率的锁相环。 发射机响应于时钟信号调整其数据传输速率以适应不同的数据传输协议。 响应于来自接收器的一个或多个信号，锁相环可以从输入时钟信号添加或丢弃周期。 来自接收机的信号指示输入数据信号的传输速率。 锁相环可以从时钟信号中降低周期，从而降低时钟信号的频率。 然后，发射机响应于时钟信号的降低的频率而降低其数据传输速率。 锁相环也可以为时钟信号添加周期以增加时钟信号的频率。 发射机响应于时钟信号的频率增加而增加其数据传输速率。

    Resistor compensation apparatus
    100.
    发明授权
    Resistor compensation apparatus 失效
    电阻补偿装置

    公开(公告)号：US07042271B2

    公开(公告)日：2006-05-09

    申请号：US10840524

    申请日：2004-05-06

    Applicant: David Kyong-Sik Chung ,  Afshin Momtaz ,  Mario Caresosa

    Inventor： David Kyong-Sik Chung ,  Afshin Momtaz ,  Mario Caresosa

    IPC: G06F7/64

    CPC classification number: H03F3/4508 ,  H03F2200/456 ,  H03F2200/465 ,  H03F2203/45292 ,  H03F2203/45541

    Abstract: A compensation apparatus maintains an effective resistance of one or more resistors in a circuit by associating an adjustable resistor circuit to each resistor. The compensation apparatus compares the resistance of a resistor in the circuit with the resistance of a reference resistor. When the resistance of the resistor in the circuit falls outside of a desired range, the compensation apparatus adjusts the resistance of the adjustable resistor to adjust the effective resistance of the resistor and adjustable resistor combination.

    Abstract translation: 补偿装置通过将可调电阻器电路与每个电阻器相关联来保持电路中的一个或多个电阻器的有效电阻。 补偿装置将电路中的电阻器的电阻与参考电阻器的电阻进行比较。 当电路中的电阻电阻超出所需范围时，补偿装置调整可调电阻的电阻，调整电阻和可调电阻组合的有效电阻。

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