公开(公告)号：US07989302B2

公开(公告)日：2011-08-02

申请号：US12795108

申请日：2010-06-07

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/20

CPC分类号： H01L29/93

摘要： Methods of forming hyper-abrupt p-n junctions and design structures for an integrated circuit containing devices structures with hyper-abrupt p-n junctions. The hyper-abrupt p-n junction is defined in a SOI substrate by implanting a portion of a device layer to have one conductivity type and then implanting a portion of this doped region to have an opposite conductivity type. The counterdoping defines the hyper-abrupt p-n junction. A gate structure carried on a top surface of the device layer operates as a hard mask during the ion implantations to assist in defining a lateral boundary for the hyper-abrupt p-n junction.

摘要翻译： 形成超突变p-n结的方法和包含具有超突变p-n结的器件结构的集成电路的设计结构。 通过将器件层的一部分注入具有一种导电类型，然后将该掺杂区域的一部分注入具有相反的导电型，在SOI衬底中限定超突变p-n结。 反渗透定义了超突变p-n结。 在离子注入期间，在器件层的顶表面上承载的栅结构作为硬掩模进行操作，以有助于限定超突变p-n结的横向边界。

公开(公告)号：US20080315266A1

公开(公告)日：2008-12-25

申请号：US11767627

申请日：2007-06-25

申请人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/80 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

摘要： A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.

摘要翻译： 结型场效应晶体管（JFET）具有作为JFET通道的超破裂结层。 超破裂结层由相反类型的两个掺杂剂分布形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。 通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的主体提供。 这与传统的JFET相反，JFET具有以与栅极相反的导电类型掺杂的主体。 主体可以通过形成在主体和衬底之间或者在主体和衬底之下的掩埋导体层之间形成的另一反向偏压接合部与衬底电耦合。 形成薄的超破裂结层的能力允许在绝缘体上半导体衬底中形成JFET。

公开(公告)号：US08216890B2

公开(公告)日：2012-07-10

申请号：US12550658

申请日：2009-08-31

申请人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

发明人： Jeffrey B. Johnson ,  Alvin J. Joseph ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L21/336

CPC分类号： H01L29/93 ,  H01L29/7391

摘要： A varactor diode includes a portion of a top semiconductor layer of a semiconductor-on-insulator (SOI) substrate and a gate electrode located thereupon. A first electrode having a doping of a first conductivity type laterally abuts a doped semiconductor region having the first conductivity type, which laterally abuts a second electrode having a doping of a second conductivity type, which is the opposite of the first conductivity type. A hyperabrupt junction is formed between the second doped semiconductor region and the second electrode. The gate electrode controls the depletion of the first and second doped semiconductor regions, thereby varying the capacitance of the varactor diode. A design structure for the varactor diode is also provided.

摘要翻译： 变容二极管包括绝缘体上半导体（SOI）衬底的顶部半导体层的一部分和位于其上的栅电极。 具有第一导电类型的掺杂的第一电极横向邻接具有第一导电类型的掺杂半导体区域，其横向邻接具有与第一导电类型相反的第二导电类型的掺杂的第二电极。 在第二掺杂半导体区域和第二电极之间形成超破坏结。 栅电极控制第一和第二掺杂半导体区的耗尽，从而改变变容二极管的电容。 还提供了变容二极管的设计结构。

公开(公告)号：US07825441B2

公开(公告)日：2010-11-02

申请号：US11767627

申请日：2007-06-25

申请人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

发明人： Ebenezer E. Eshun ,  Jeffrey B. Johnson ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

IPC分类号： H01L29/808 ,  H01L21/337

CPC分类号： H01L29/808 ,  H01L27/0617 ,  H01L27/098 ,  H01L29/36 ,  H01L29/66901

摘要： A junction field effect transistor (JFET) has a hyperabrupt junction layer that functions as a channel of a JFET. The hyperabrupt junction layer is formed by two dopant profiles of opposite types such that one dopant concentration profile has a peak concentration depth at a tail end of the other dopant profile. The voltage bias to the channel is provided by a body that is doped with the same type of dopants as the gate. This is in contrast with conventional JFETs that have a body that is doped with the opposite conductivity type as the gate. The body may be electrically decoupled from the substrate by another reverse bias junction formed either between the body and the substrate or between a buried conductor layer beneath the body and the substrate. The capability to form a thin hyperabrupt junction layer allows formation of a JFET in a semiconductor-on-insulator substrate.

摘要翻译： 结型场效应晶体管（JFET）具有作为JFET通道的超破裂结层。 超破裂结层由相反类型的两个掺杂剂分布形成，使得一个掺杂剂浓度分布在另一个掺杂剂分布的尾端处具有峰值浓度深度。 通道的电压偏置由掺杂有与栅极相同类型的掺杂剂的主体提供。 这与传统的JFET相反，JFET具有以与栅极相反的导电类型掺杂的主体。 主体可以通过形成在主体和衬底之间或者在主体和衬底之下的掩埋导体层之间形成的另一反向偏压接合部与衬底电耦合。 形成薄的超破裂结层的能力允许在绝缘体上半导体衬底中形成JFET。

公开(公告)号：US08871600B2

公开(公告)日：2014-10-28

申请号：US13294760

申请日：2011-11-11

申请人： David L. Harame ,  Qizhi Liu ,  Robert M. Rassel

发明人： David L. Harame ,  Qizhi Liu ,  Robert M. Rassel

IPC分类号： H01L21/8222 ,  H01L29/47 ,  H01L27/07 ,  H01L29/66 ,  H01L29/732 ,  H01L29/872 ,  H01L29/08 ,  H01L29/161

CPC分类号： H01L29/0684 ,  H01L27/0766 ,  H01L29/0821 ,  H01L29/161 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66234 ,  H01L29/7322 ,  H01L29/872

摘要： Schottky barrier diodes, methods for fabricating Schottky barrier diodes, and design structures for a Schottky barrier diode. A guard ring for a Schottky barrier diode is formed with a selective epitaxial growth process. The guard ring for the Schottky barrier diode and an extrinsic base of a vertical bipolar junction diode on a different device region than the Schottky barrier diode may be concurrently formed using the same selective epitaxial growth process.

摘要翻译： 肖特基势垒二极管，肖特基势垒二极管的制造方法以及肖特基势垒二极管的设计结构。 用选择性外延生长工艺形成用于肖特基势垒二极管的保护环。 可以使用相同的选择性外延生长工艺同时形成用于肖特基势垒二极管的保护环和与肖特基势垒二极管不同的器件区上的垂直双极结二极管的外部基极。

公开(公告)号：US08618588B2

公开(公告)日：2013-12-31

申请号：US12915888

申请日：2010-10-29

申请人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

发明人： Kristin M. Ackerson ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Richard J. Rassel ,  Robert M. Rassel

IPC分类号： H01L31/062 ,  H01L31/113

CPC分类号： H04N5/238 ,  H01L27/14623 ,  H01L27/14625 ,  H01L27/14685 ,  H04N5/3591

摘要： A method of preventing blooming in a pixel array includes affecting an amount of light that impinges on a photoelectric conversion element by adjusting a transmissivity of an electrochromic element based on an output of the photoelectric conversion element.

摘要翻译： 防止像素阵列中的起霜的方法包括通过基于光电转换元件的输出调节电致变色元件的透射率来影响照射到光电转换元件上的光量。

公开(公告)号：US08519478B2

公开(公告)日：2013-08-27

申请号：US13019716

申请日：2011-02-02

申请人： Robert M. Rassel ,  Mark E. Stidham

发明人： Robert M. Rassel ,  Mark E. Stidham

IPC分类号： H01L29/06

CPC分类号： H01L29/66143 ,  G06F17/5068 ,  H01L29/872

摘要： Disclosed are embodiments of a Schottky barrier diode. This diode can be formed in a semiconductor substrate having a doped region with a first conductivity type. A trench isolation structure can laterally surround a section of the doped region at the top surface of the substrate. A semiconductor layer can be positioned on the top surface of the substrate. This semiconductor layer can have a Schottky barrier portion over the defined section of the doped region and a guardring portion over the trench isolation structure laterally surrounding the Schottky barrier portion. The Schottky barrier portion can have the first conductivity type and the guarding portion can have a second conductivity type different from the first conductivity type. A metal silicide layer can overlie the semiconductor layer. Also disclosed are embodiments of a method of forming this Schottky barrier diode and of a design structure for the Schottky barrier diode.

摘要翻译： 公开了肖特基势垒二极管的实施例。 该二极管可以形成在具有第一导电类型的掺杂区域的半导体衬底中。 沟槽隔离结构可以横向围绕衬底顶表面处的掺杂区域的一部分。 半导体层可以位于衬底的顶表面上。 该半导体层可以在掺杂区域的限定部分上方具有肖特基势垒部分，并且在沟槽隔离结构之上的护套部分横向围绕肖特基势垒部分。 肖特基势垒部分可以具有第一导电类型，并且防护部分可以具有不同于第一导电类型的第二导电类型。 金属硅化物层可以覆盖半导体层。 还公开了形成该肖特基势垒二极管的方法和肖特基势垒二极管的设计结构的实施例。

公开(公告)号：US08518782B2

公开(公告)日：2013-08-27

申请号：US12963054

申请日：2010-12-08

申请人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark E. Stidham

发明人： Alan B. Botula ,  Robert M. Rassel ,  Yun Shi ,  Mark E. Stidham

IPC分类号： H01L21/426

CPC分类号： H01L29/7833 ,  H01L21/26586 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including a first source drain region, a second source drain region, and an intrinsic region therebetween; an asymmetric lightly doped drain (LDD) region within the substrate, wherein the asymmetric LDD region extends from the first source drain region into the intrinsic region between the first source drain region and the second source drain region; and a gate positioned atop the semiconductor substrate, wherein an outer edge of the gate overlaps the second source drain region. A related method and design structure are also disclosed.

摘要翻译： 公开了一种半导体器件。 半导体器件包括：半导体衬底，包括第一源极漏极区域，第二源极漏极区域及其之间的固有区域; 在所述衬底内的不对称轻掺杂漏极（LDD）区域，其中所述不对称LDD区域从所述第一源极漏极区域延伸到所述第一源极漏极区域和所述第二源极漏极区域之间的本征区域; 以及位于所述半导体衬底顶部的栅极，其中所述栅极的外边缘与所述第二源极漏极区重叠。 还公开了相关的方法和设计结构。

公开(公告)号：US08466501B2

公开(公告)日：2013-06-18

申请号：US12784583

申请日：2010-05-21

申请人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

发明人： Douglas B. Hershberger ,  Richard A. Phelps ,  Robert M. Rassel ,  Stephen A. St. Onge ,  Michael J. Zierak

IPC分类号： H01L29/808

CPC分类号： G06F17/5068 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/66901 ,  H01L29/8086

摘要： An asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method. The JFET includes a bottom gate on an insulator layer, a channel region on the bottom gate and, on the channel region, source/drain regions and a top gate between the source/drain regions. STIs isolate the source/drain regions from the top gate and a DTI laterally surrounds the JFET to isolate it from other devices. Non-annular well(s) are positioned adjacent to the channel region and bottom gate (e.g., a well having the same conductivity type as the top and bottom gates can be connected to the top gate and can extend down to the insulator layer, forming a gate contact on only a portion of the channel region, and/or another well having the same conductivity type as the channel and source/drain regions can extend from the source region to the insulator layer, forming a source-to-channel strap).

摘要翻译： 不对称绝缘体上硅（SOI）结场效应晶体管（JFET）及其方法。 JFET包括在绝缘体层上的底栅极，底栅上的沟道区，以及沟道区上的源/漏区和源/漏区之间的顶栅。 STI将源极/漏极区域与顶部栅极隔离，并且DTI横向围绕JFET以将其与其它器件隔离。 非环形阱位于与沟道区域和底部栅极相邻的位置（例如，具有与顶部和底部栅极相同的导电类型的阱可以连接到顶部栅极并且可以向下延伸到绝缘体层，形成 在沟道区域的仅一部分上的栅极接触和/或具有与沟道和源极/漏极区相同的导电类型的另一个阱可以从源极区域延伸到绝缘体层，形成源极至沟道的带） 。

公开(公告)号：US20130140668A1

公开(公告)日：2013-06-06

申请号：US13312442

申请日：2011-12-06

申请人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

发明人： Alan B. Botula ,  Renata Camillo-Castillo ,  James S. Dunn ,  Jeffrey P. Gambino ,  Douglas B. Hershberger ,  Alvin J. Joseph ,  Mark E. Stidham ,  Robert M. Rassel

IPC分类号： H01L27/04 ,  H01L21/76

CPC分类号： H01L21/76224 ,  H01L21/26506 ,  H01L21/823892 ,  H01L27/04 ,  H01L27/0623 ,  H01L27/0635 ,  H01L27/0802 ,  H01L27/0811 ,  H01L27/0928

摘要： A substrate includes a first region having a first resistivity, for optimizing a field effect transistor, a second region having a second resistivity, for optimizing an npn subcollector of a bipolar transistor device and triple well, a third region having a third resistivity, with a high resistivity for a passive device, a fourth region, substantially without implantation, to provide low perimeter capacitance for devices.

摘要翻译： 衬底包括具有第一电阻率的第一区域，用于优化场效应晶体管，具有第二电阻率的第二区域，用于优化双极晶体管器件和三阱的npn子集电极，具有第三电阻率的第三区域，具有第三电阻率 用于无源器件的高电阻率，第四区域，基本上没有植入，以为器件提供低周边电容。