公开(公告)号：US08994082B2

公开(公告)日：2015-03-31

申请号：US13250856

申请日：2011-09-30

申请人： Feng-Chi Hung ,  Jhy-Jyi Sze ,  Shou-Gwo Wuu

发明人： Feng-Chi Hung ,  Jhy-Jyi Sze ,  Shou-Gwo Wuu

IPC分类号： H01L31/062 ,  H01L31/113 ,  H01L21/265 ,  H01L29/78 ,  H01L27/146 ,  H01L21/28

CPC分类号： H01L27/14616 ,  H01L21/0223 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28123 ,  H01L21/2822 ,  H01L21/76224 ,  H01L27/14603 ,  H01L27/14612 ,  H01L27/1463 ,  H01L29/0653 ,  H01L29/41775 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/78

摘要： Transistors, methods of manufacturing thereof, and image sensor circuits with reduced random telegraph signal (RTS) noise are disclosed. In one embodiment, a transistor includes a channel disposed between two isolation regions in a workpiece. The channel has edge regions proximate the isolation regions and a central region between the edge regions. The transistor includes a gate dielectric disposed over the channel, and a gate disposed over the gate dielectric. The transistor includes a voltage threshold modification feature proximate the edge regions configured to increase a voltage threshold of the transistor proximate edge regions relative to the central region of the channel.

摘要翻译： 公开了晶体管，其制造方法和具有减少的随机电报信号（RTS）噪声的图像传感器电路。 在一个实施例中，晶体管包括设置在工件中的两个隔离区域之间的通道。 通道具有靠近隔离区域的边缘区域和边缘区域之间的中心区域。 晶体管包括设置在通道上方的栅极电介质和设置在栅极电介质上的栅极。 晶体管包括靠近边缘区域的电压阈值修改特征，其被配置成相对于通道的中心区域增加晶体管的边缘区域的电压阈值。

公开(公告)号：US08216905B2

公开(公告)日：2012-07-10

申请号：US12768063

申请日：2010-04-27

申请人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

发明人： Ru-Shang Hsiao ,  Nai-Wen Cheng ,  Chung-Te Lin ,  Chien-Hsien Tseng ,  Shou-Gwo Wuu

IPC分类号： H01L21/336

CPC分类号： H01L27/1463 ,  H01L21/324 ,  H01L21/823878 ,  H01L22/34 ,  H01L27/14689 ,  H01L29/7842

摘要： The active pixel cell structures and methods of preparing such structures described above enable reduction of dark current and white cell counts for active pixel cells. The process of preparing active pixel cell structures introduces stress on the substrate, which could lead to increased dark current and white cell counts of active pixel cells. By depositing a stress layer as part of a pre-metal dielectric layer with a stress that counters the stress induced, both the dark current and the white cell counts can be reduced. If the transistors of the active pixel cells are NMOS, the carrier mobility can also be increased by a tensile stress layer. Raman Spectroscopy can be used to measure the stress exerted on the substrate prior to the deposition of the stress layer.

摘要翻译： 上述有源像素单元结构和制备这种结构的方法能够减少有源像素单元的暗电流和白细胞计数。 制备有源像素单元结构的过程在衬底上引入应力，这可能导致有源像素单元的暗电流和白细胞计数增加。 通过沉积应力层作为预金属介电层的一部分，其应力引起应力，暗电流和白细胞计数都可以减小。 如果有源像素单元的晶体管是NMOS，则载流子迁移率也可以通过拉伸应力层增加。 拉曼光谱可用于测量在沉积应力层之前施加在基底上的应力。

公开(公告)号：US20080265242A1

公开(公告)日：2008-10-30

申请号：US11739650

申请日：2007-04-24

申请人： Shine Chung ,  Shou-Gwo Wuu

发明人： Shine Chung ,  Shou-Gwo Wuu

IPC分类号： H01L29/66

CPC分类号： H01L27/14632 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14645 ,  H01L27/14663 ,  H01L27/14696

摘要： A photosensitive device is disclosed which comprises a semiconductor substrate, at least one reverse biased device, such as a P-N junction diode formed in the semiconductor substrate, and at least one photosensitive layer disposed above the semiconductor substrate and substantially covering the reverse biased device, the photosensitive layer releasing electrons and holes when struck by photons, wherein the photon generated electrons and holes in the photosensitive layer reach the reverse biased device and create a combination current therein when a light shines thereon.

摘要翻译： 公开了一种光敏器件，其包括半导体衬底，形成在半导体衬底中的至少一个反向偏压器件，例如PN结二极管，以及设置在半导体衬底之上并基本上覆盖反向偏置器件的至少一个感光层， 光敏层在被光子撞击时释放电子和空穴，其中光子产生的电子和感光层中的空穴到达反向偏置器件，并且当光照射在其上时产生组合电流。

公开(公告)号：US20080105944A1

公开(公告)日：2008-05-08

申请号：US11682350

申请日：2007-03-06

申请人： Chung-Wei Chang ,  Han-Chi Liu ,  Chun-Yao Ko ,  Shou-Gwo Wuu

发明人： Chung-Wei Chang ,  Han-Chi Liu ,  Chun-Yao Ko ,  Shou-Gwo Wuu

IPC分类号： H01L31/06 ,  H01L31/068

CPC分类号： H01L27/1463 ,  H01L21/761 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/035272

摘要： The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.

摘要翻译： 本公开提供了一种图像传感器半导体器件。 半导体器件包括具有第一类掺杂剂的半导体衬底; 半导体层，其具有不同于所述第一类型掺杂剂的第二类型的掺杂剂并且设置在所述半导体衬底上; 以及形成在半导体层中的图像传感器。

公开(公告)号：US06335249B1

公开(公告)日：2002-01-01

申请号：US09498981

申请日：2000-02-07

申请人： Kong-Beng Thei ,  Ming-Ta Lei ,  Shou-Gwo Wuu

发明人： Kong-Beng Thei ,  Ming-Ta Lei ,  Shou-Gwo Wuu

IPC分类号： H01L21336

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L29/665

摘要： A process for making improved borderless contact structure to salicide field effect transistors (FETs) has been achieved. Salicide FETs are formed on device areas surrounded by a shallow trench isolation (STI) using a first rapid thermal anneal (RTA-1) to form a metal silicide on the source/drain contacts and the gate electrodes, and a second rapid thermal anneal (RTA-2) is delayed until after forming a borderless contact opening structures to the source/drain areas of the FETs. An etch stop (Si3N4) layer and an interlevel dielectric (ILD) layer is deposited, and borderless contact openings, extending over the STI, are etched in the ILD and etch stop layers to the source/drain areas. The contact openings across the substrate must be over-etched to insure that all contacts are open. This results in over-etched region in the STI at the source/drain-STI interface that result in source/drain-to-substrate shorts when metal plugs are formed in the contact openings.

摘要翻译： 已经实现了对自对准硅化物场效应晶体管（FET）进行改进的无边界接触结构的方法。 使用第一快速热退火（RTA-1）在由浅沟槽隔离（STI）围绕的器件区域上形成硅化物FET，以在源/漏接触和栅电极上形成金属硅化物，以及第二快速热退火 RTA-2）延迟直到形成无界面接触开口结构到FET的源极/漏极区域。 沉积蚀刻停止层（Si3N4）层和层间电介质（ILD）层，并且在IL上延伸的无边界接触开口在ILD中蚀刻，并将停止层蚀刻到源极/漏极区域。 必须对衬底上的接触孔进行过蚀刻，以确保所有接触都是开放的。 这导致在源极/漏极-CS接口处的STI中的过蚀刻区域，当在接触开口中形成金属插塞时，其导致源极/漏极到衬底短路。

公开(公告)号：US5834342A

公开(公告)日：1998-11-10

申请号：US884917

申请日：1997-06-30

申请人： Kan-Yuan Lee ,  Shou-Gwo Wuu ,  Dun-Nian Yang

发明人： Kan-Yuan Lee ,  Shou-Gwo Wuu ,  Dun-Nian Yang

IPC分类号： H01L21/336 ,  H01L21/8244 ,  H01L29/417 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/66765 ,  H01L27/11 ,  H01L29/41733 ,  H01L29/78624

摘要： A process for manufacturing a thin film transistor for use in a CMOS SRAM circuit is described. A key feature is the formation of two different photoresist masks from the same optical mask. The first photoresist mask is generated using a normal amount of actinic radiation during exposure and is used to protect the gate region during source and drain formation through ion implantation. The second photoresist mask is aligned relative to the gate in exactly the same orientation as the first mask but is given a reduced exposure of actinic radiation. This results, after development, in a slightly larger mask which is used during etching to form the oxide cap that will protect the channel area during the subsequent silicidation step. Making the cap slightly wider than the channel ensures that small lengths of the source and the drain regions that abut the channel are not converted to silicide. Thus, the finished device continues to act as a thin film transistor, but has greatly reduced source and drain resistances.

摘要翻译： 描述用于制造用于CMOS SRAM电路的薄膜晶体管的工艺。 一个关键特征是从相同的光学掩模形成两种不同的光刻胶掩模。 在曝光期间使用正常量的光化辐射产生第一光致抗蚀剂掩模，并且用于通过离子注入在源极和漏极形成期间保护栅极区域。 第二光致抗蚀剂掩模相对于栅极以与第一掩模完全相同的取向对准，但被给予光化辐射的减少的曝光。 这在显影之后产生了在蚀刻期间用于形成氧化物盖的稍大的掩模，其将在随后的硅化步骤期间保护沟道区域。 使帽子比通道略宽，确保抵靠通道的源极和漏极区域的较小长度不会转化为硅化物。 因此，成品器件继续作为薄膜晶体管，但是极大地降低了源极和漏极电阻。

公开(公告)号：US5731232A

公开(公告)日：1998-03-24

申请号：US745639

申请日：1996-11-08

申请人： Shou-Gwo Wuu ,  Mong-Song Liang

发明人： Shou-Gwo Wuu ,  Mong-Song Liang

IPC分类号： H01L21/84 ,  H01L21/00

CPC分类号： H01L21/84 ,  Y10S257/903

摘要： A method is achieved for making TFT-load static random access memory (SRAM) cells where the thin film transistor (TFT) gate electrodes are made from an electrical conductor. At the same time, portions of the conductor between P and N doped polysilicon interconnections eliminate the P/N junction. Ohmic contacts are formed while avoiding additional processing steps. N-channel FET gate electrodes are formed from an N.sup.+ doped first polysilicon layer having a first insulating layer thereon. Second polySi interconnections are formed with a second insulating layer thereon. First contact openings are etched in the first and second insulating layers to the N.sup.+ doped FET gate electrodes, and a patterned conductor (TiN, TiSi.sub.2) forms the P-channel TFT gate electrodes and concurrently forms portions over and in the first contact openings. A TFT gate oxide is formed and second contact openings are etched over the first contact openings to the conductor. An N.sup.- doped third polySi layer is deposited, selectively doped P.sup.+ and patterned to form the TFT N.sup.- doped channel, the P.sup.+ doped source/drains, and the interconnection in the contact openings to the N-FET gate electrodes. The conductor at the interface between the P/N polySi forms essentially ohmic contacts, thereby eliminating the P/N junction and improving circuit performance.

摘要翻译： 实现了薄膜晶体管（TFT）栅电极由电导体制成的TFT负载静态随机存取存储器（SRAM）单元的方法。 同时，P和N掺杂多晶硅互连之间的导体部分消除了P / N结。 在避免额外的处理步骤的同时形成欧姆接触。 N沟道FET栅极由其上具有第一绝缘层的N +掺杂的第一多晶硅层形成。 第二多晶硅互连在其上形成有第二绝缘层。 第一接触开口在第一和第二绝缘层中蚀刻到N +掺杂FET栅电极，并且图案化导体（TiN，TiSi 2）形成P沟道TFT栅电极，同时在第一接触开口上并在其中形成部分。 形成TFT栅极氧化物，并且第二接触开口在第一接触开口上蚀刻到导体。 沉积N-掺杂的第三多晶硅层，选择性掺杂P +并图案化以形成TFT N掺杂沟道，P +掺杂源极/漏极以及在N-FET栅电极的接触开口中的互连。 在P / N多晶硅之间的界面处的导体形成基本的欧姆接触，从而消除P / N结并提高电路性能。

公开(公告)号：US5607879A

公开(公告)日：1997-03-04

申请号：US496019

申请日：1995-06-28

申请人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

发明人： Shou-Gwo Wuu ,  Chen-Jong Wang ,  Mong-Song Liang ,  Chung-Hui Su

IPC分类号： H01L21/311 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L21/28

CPC分类号： H01L21/76897 ,  H01L21/31116 ,  H01L21/76801 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for fabricating buried metal plug structures for multi-polysilicon layer interconnects and for concurrently making metal plugs on semiconductor integrated circuits, such as DRAM and SRAM, was achieved. The method involved forming contact opening in an insulating layer over opening in a patterned polysilicon layer. The opening in the polysilicon layer aligned over source/drain contact areas on the substrate and providing a means for forming self-aligned contact openings. Buried metal plugs in the contact openings form interconnects between the polysilicon layer and the source/drains. And, by merging the process steps, concurrently forming metal plug interconnects for contacts to semiconductor devices and first level metal. The process is applicable to the formation of bit line contacts on DRAM and SRAM circuits and simultaneously form the peripheral contact on the chip.

公开(公告)号：US5587696A

公开(公告)日：1996-12-24

申请号：US496018

申请日：1995-06-28

申请人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

发明人： Chung-Hui Su ,  Mong-Song Liang ,  Shou-Gwo Wuu ,  Chen-Jong Wang

IPC分类号： H01L21/02 ,  H01C1/012

CPC分类号： H01L28/20 ,  Y10T29/49082

摘要： A multi-layer polysilicon resistor and a method by which the multi-layer polysilicon resistor is formed. A minimum of two polysilicon layers is formed upon an insulating layer, the insulating layer in turn being formed upon a semiconductor substrate. The first polysilicon layer is formed to a first thickness at a first deposition temperature. The second polysilicon layer is formed directly upon the first polysilicon layer. The second polysilicon layer is formed to a second thickness at a second deposition temperature. The two deposition temperatures are in the range of about 450 degrees centigrade to about 620 degrees centigrade, and the difference in temperature between the first deposition temperature and the second deposition temperature is a minimum of 10 degrees centigrade.

摘要翻译： 多层多晶硅电阻器和形成多层多晶硅电阻器的方法。 在绝缘层上形成至少两个多晶硅层，绝缘层依次形成在半导体衬底上。 第一多晶硅层在第一沉积温度下形成第一厚度。 第二多晶硅层直接形成在第一多晶硅层上。 第二多晶硅层在第二沉积温度下形成第二厚度。 两个沉积温度在约450摄氏度至约620摄氏度的范围内，并且第一沉积温度和第二沉积温度之间的温度差最小为10摄氏度。

公开(公告)号：US09257463B2

公开(公告)日：2016-02-09

申请号：US13588879

申请日：2012-08-17

申请人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

发明人： Chien-Hsien Tseng ,  Shou-Gwo Wuu ,  Chia-Chan Chen ,  Kuo-Yu Wu ,  Dao-Hong Yang ,  Ming-Hao Chung

IPC分类号： H01L21/336 ,  H01L27/146

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/1463

摘要： A device includes a semiconductor substrate, a well region in the semiconductor substrate, and a Metal-Oxide-Semiconductor (MOS) device. The MOS device includes a gate dielectric overlapping the well region, a gate electrode over the gate dielectric, and a source/drain region in the well region. The source/drain region and the well region are of opposite conductivity types. An edge of the first source drain region facing away from the gate electrode is in contact with the well region to form a junction isolation.

摘要翻译： 一种器件包括半导体衬底，半导体衬底中的阱区和金属氧化物半导体（MOS）器件。 MOS器件包括与阱区重叠的栅极电介质，栅极电介质上的栅电极和阱区中的源极/漏极区。 源/漏区和阱区具有相反的导电类型。 第一源漏区域背离栅电极的边缘与阱区域接触以形成结隔离。