公开(公告)号：US08377787B2

公开(公告)日：2013-02-19

申请号：US13155957

申请日：2011-06-08

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

摘要翻译： 提供半导体器件。 在一个实施例中，该器件包括形成在半导体衬底上的衬底和晶体管。 晶体管可以包括栅极结构，源极区和漏极区。 漏极区域包括交替掺杂分布区域。 交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。 在一个实施例中，晶体管是高压晶体管。

公开(公告)号：US20130020636A1

公开(公告)日：2013-01-24

申请号：US13185951

申请日：2011-07-19

申请人： Tsung-Yi Huang

发明人： Tsung-Yi Huang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0878 ,  H01L29/0696 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816

摘要： The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a well of a substrate. The high voltage device includes: a field oxide region; a gate, which is formed on a surface of the substrate, and part of the gate is located above the field oxide region; a source and a drain, which are formed at two sides of the gate respectively; and a first low concentration doped region, which is formed beneath the gate and has an impurity concentration which is lower than that of the well surrounded, wherein from top view, the first low concentration doped region has an area within the gate and not larger than an area of the gate, and the first low concentration doped region has a depth which is deeper than that of the source and drain.

摘要翻译： 本发明公开了一种高压器件及其制造方法。 高压器件形成在衬底的阱中。 高电压装置包括：场氧化物区域; 栅极，其形成在基板的表面上，栅极的一部分位于场氧化物区域的上方; 源极和漏极，分别形成在栅极的两侧; 以及第一低浓度掺杂区，其形成在栅极下方并且具有低于所围绕的阱的杂质浓度，其中从顶视图来看，第一低浓度掺杂区具有栅极内的面积并且不大于 栅极的面积，第一低浓度掺杂区域的深度比源极和漏极深。

公开(公告)号：US20110309443A1

公开(公告)日：2011-12-22

申请号：US12817413

申请日：2010-06-17

申请人： Tsung-Yi Huang ,  Ying-Shiou Lin

发明人： Tsung-Yi Huang ,  Ying-Shiou Lin

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L21/265

CPC分类号： H01L29/7835 ,  H01L21/26513 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/66659

摘要： The present invention discloses a method for controlling the impurity density distribution in semiconductor device and a semiconductor device made thereby. The control method includes the steps of: providing a substrate; defining a doped area which includes at least one first region; partially masking the first region by a mask pattern; and doping impurities in the doped area to form one integrated doped region in the first region, whereby the impurity concentration of the first region is lower than a case where the first region is not masked by the mask pattern.

摘要翻译： 本发明公开了一种用于控制半导体器件中的杂质浓度分布的方法和由此制成的半导体器件。 控制方法包括以下步骤：提供基板; 限定包括至少一个第一区域的掺杂区域; 通过掩模图案部分地掩蔽所述第一区域; 以及在所述掺杂区域中掺杂杂质以在所述第一区域中形成一个积分掺杂区域，由此所述第一区域的杂质浓度低于所述第一区域未被所述掩模图案掩蔽的情况。

公开(公告)号：US20110237041A1

公开(公告)日：2011-09-29

申请号：US13155957

申请日：2011-06-08

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Fei-Yuh Chen ,  Tsung-Yi Huang

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/66659 ,  H01L29/7835

摘要： A semiconductor device is provided. In an embodiment, the device includes a substrate and a transistor formed on the semiconductor substrate. The transistor may include a gate structure, a source region, and a drain region. The drain region includes an alternating-doping profile region. The alternating-doping profile region may include alternating regions of high and low concentrations of a dopant. In an embodiment, the transistor is a high voltage transistor.

摘要翻译： 提供半导体器件。 在一个实施例中，该器件包括形成在半导体衬底上的衬底和晶体管。 晶体管可以包括栅极结构，源极区和漏极区。 漏极区域包括交替掺杂分布区域。 交变掺杂剖面区域可以包括掺杂剂的高浓度和低浓度的交替区域。 在一个实施例中，晶体管是高压晶体管。

公开(公告)号：US07888734B2

公开(公告)日：2011-02-15

申请号：US12328277

申请日：2008-12-04

申请人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

发明人： Chen-Liang Chu ,  Chun-Ting Liao ,  Tsung-Yi Huang ,  Fei-Yuh Chen

IPC分类号： H01L29/66

CPC分类号： H01L29/7833 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/66621 ,  H01L29/66659 ,  H01L29/7835

摘要： An integrated circuit structure includes a high-voltage well (HVW) region in a semiconductor substrate; a first double diffusion (DD) region in the HVW region; and a second DD region in the HVW region. The first DD region and the second DD region are spaced apart from each other by an intermediate portion of the HVW region. A recess extends from a top surface of the semiconductor substrate into the intermediate portion of the HVW region and the second DD region. A gate dielectric extends into the recess and covers a bottom of the recess. A gate electrode is over the gate dielectric. A first source/drain region is in the first DD region. A second source/drain region is in the second DD region.

摘要翻译： 集成电路结构包括半导体衬底中的高电压阱（HVW）区域; HVW区域中的第一双扩散（DD）区域; 和HVW区域中的第二DD区域。 第一DD区域和第二DD区域通过HVW区域的中间部分彼此间隔开。 凹部从半导体衬底的顶表面延伸到HVW区域和第二DD区域的中间部分。 栅极电介质延伸到凹部中并覆盖凹部的底部。 栅极电极在栅极电介质上方。 第一源/漏区在第一DD区。 第二个源极/漏极区域位于第二个DD区域。

公开(公告)号：US20110006366A1

公开(公告)日：2011-01-13

申请号：US12887300

申请日：2010-09-21

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L29/78

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US07816214B2

公开(公告)日：2010-10-19

申请号：US12362307

申请日：2009-01-29

申请人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

发明人： Hsueh-Liang Chou ,  Chen-Bau Wu ,  Weng-Chu Chu ,  Tsung-Yi Huang ,  Fu-Jier Fan

IPC分类号： H01L21/8234

CPC分类号： H01L29/66477 ,  H01L21/28 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/8611

摘要： A semiconductor structure includes a substrate, a first well region of a first conductivity type overlying the substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate, a cushion region between and adjoining the first and the second well regions, an insulation region in a portion of the first well region and extending from a top surface of the first well region into the first well region, a gate dielectric extending from over the first well region to over the second well region, wherein the gate dielectric has a portion over the insulation region, and a gate electrode on the gate dielectric.

摘要翻译： 半导体结构包括衬底，覆盖衬底的第一导电类型的第一阱区，覆盖衬底的与第一导电类型相反的第二导电类型的第二阱区，与第一阱和第二阱相邻的衬垫区 区域，在所述第一阱区域的一部分中并且从所述第一阱区域的顶表面延伸到所述第一阱区域中的绝缘区域;从所述第一阱区域延伸到所述第二阱区域的栅极电介质，其中所述栅极 电介质具有绝缘区域上的一部分，以及栅极电介质上的栅电极。

公开(公告)号：US20100096697A1

公开(公告)日：2010-04-22

申请号：US12256009

申请日：2008-10-22

申请人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

发明人： Ru-Yi Su ,  Pou-Yu Chiang ,  Jeng Gong ,  Tsung-Yi Huang ,  Chun Lin Tsai ,  Chien-Chih Chou

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7835

摘要： A semiconductor device includes a semiconductor substrate, a source region and a drain region formed in the substrate, a gate structure formed on the substrate disposed between the source and drain regions, and a first isolation structure formed in the substrate between the gate structure and the drain region, the first isolation structure including projections that are located proximate to an edge of the drain region. Each projection includes a width measured in a first direction along the edge of the drain region and a length measured in a second direction perpendicular to the first direction, and adjacent projections are spaced a distance from each other.

摘要翻译： 半导体器件包括半导体衬底，形成在衬底中的源极区和漏极区，形成在衬底上的栅极结构，该衬底设置在源极和漏极区之间，第一隔离结构形成在栅极结构和栅极结构之间的衬底中 漏极区域，所述第一隔离结构包括位于所述漏极区域的边缘附近的突起。 每个突起包括在沿着漏极区域的边缘的第一方向上测量的宽度和在垂直于第一方向的第二方向上测量的长度，并且相邻的突起彼此间隔一定距离。

公开(公告)号：US07423319B2

公开(公告)日：2008-09-09

申请号：US11646683

申请日：2006-12-28

申请人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

发明人： Robin Hsieh ,  Tsai Chun Lin ,  Albert Yao ,  Pai-Kang Hsu ,  Tsung-Yi Huang ,  Ruey-Hsin Liu

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659

摘要： A semiconductor structure includes a first well region of a first conductivity type overlying a substrate, a second well region of a second conductivity type opposite the first conductivity type overlying the substrate and laterally adjoining the first well region, a third well region of the second conductivity type adjacent and spaced apart from the first well region, a first deep well region of the second conductivity type underlying at least portions of the first and the second well regions, a second deep well region of the second conductivity type underlying the third well region and spaced apart from the first deep well region, an insulation region in the first well region, a gate dielectric extending from over the insulation region to over the second well region, and a gate electrode on the gate dielectric.

公开(公告)号：US20060006462A1

公开(公告)日：2006-01-12

申请号：US11122635

申请日：2005-05-05

申请人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

发明人： Chi-Hsuen Chang ,  Jun Liu ,  Tsung-Yi Huang ,  Chung-I Chen ,  Tzu-Chiang Sung ,  Chih Huang ,  Rann Yeh

IPC分类号： H01L29/76

CPC分类号： H01L21/76229 ,  H01L21/76232 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7391 ,  H01L29/7816

摘要： Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

摘要翻译： 描述了包括高压MOS晶体管的半导体器件的方法和装置。 衬底设置有彼此分离的低电压和高电压区域。 形成包含绝缘体的隔离区，包括形成在高电压区域内的所述阱内的至少一个。 从高电压装置区域中的有源区域到隔离区域的转变角度大于预定角度，在一些实施例中，它与垂直方向大于40度。 在一些实施例中，使用浅沟槽隔离技术形成隔离区域。 在替代实施例中，使用通过硅技术的局部氧化形成的场氧化物形成隔离区。