公开(公告)号：US12243923B2

公开(公告)日：2025-03-04

申请号：US17506992

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Venkata N. R. Vanukuru ,  Mark Levy

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/10

Abstract: Structures for a transistor including regions for landing gate contacts and methods of forming a structure for a transistor that includes regions for landing gate contacts. The structure includes a field-effect transistor having a source region, a gate region, a gate with a sidewall, and a gate extension with a section adjoined to the sidewall. The structure further includes a dielectric layer over the field-effect transistor, and a gate contact positioned in the dielectric layer to land on at least the section of the gate extension.

公开(公告)号：US20230317776A1

公开(公告)日：2023-10-05

申请号：US17708561

申请日：2022-03-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Michel Abou-Khalil ,  Steven M. Shank ,  Aaron Vallett ,  Sarah McTaggart ,  Rajendran Krishnasamy

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/0649 ,  H01L29/4236 ,  H01L29/1087

Abstract: Semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation. The structure includes a semiconductor substrate having a first surface, a recess in the first surface, and a second surface inside the first recess. The structure further includes a shallow trench isolation region extending from the first surface into the semiconductor substrate. The shallow trench isolation region is positioned to surround an active device region including the recess. A field-effect transistor includes a gate electrode positioned on a portion of the second surface.

公开(公告)号：US11764060B2

公开(公告)日：2023-09-19

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L21/02667 ,  H01L21/26506 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1079 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/78 ,  H01L21/02532 ,  H01L21/02595

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US11664412B2

公开(公告)日：2023-05-30

申请号：US17155445

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L21/762 ,  H01L27/06 ,  H01L49/02

CPC classification number: H01L28/20 ,  H01L21/76224 ,  H01L27/0629

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.

公开(公告)号：US11637173B2

公开(公告)日：2023-04-25

申请号：US17036194

申请日：2020-09-29

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yves T. Ngu ,  Siva P. Adusumilli ,  Steven M. Shank ,  Michael J. Zierak ,  Mickey H. Yu

IPC: H01L49/02 ,  H01L27/12 ,  H01L21/3215 ,  C30B29/06

Abstract: A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

公开(公告)号：US20230096544A1

公开(公告)日：2023-03-30

申请号：US17449336

申请日：2021-09-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uzma B. Rana ,  Steven M. Shank ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/762 ,  H01L21/763

Abstract: A transistor includes a bulk semiconductor substrate, and first and second raised source/drain regions above the bulk semiconductor substrate. A gate is between the first and second raised source/drain regions. A first dielectric section is beneath the first raised source/drain region in the bulk semiconductor substrate, and a second dielectric section is beneath the second raised source/drain region in the bulk semiconductor substrate. A first air gap is defined in at least the first dielectric section under the first raised source/drain region, and a second air gap is defined in at least the second dielectric section under the second raised source/drain region. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US20230088425A1

公开(公告)日：2023-03-23

申请号：US17483104

申请日：2021-09-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ephrem G. Gebreselasie ,  Steven M. Shank ,  Alain F. Loiseau ,  Robert J. Gauthier, JR. ,  Michel J. Abou-Khalil ,  Ahmed Y. Ginawi

IPC: H01L27/06 ,  H01L21/8234 ,  H01L23/525

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an eFuse and gate structure on a triple-well and methods of manufacture. The structure includes: a substrate comprising a bounded region; a gate structure formed within the bounded region; and an eFuse formed within the bounded region and electrically connected to the gate structure.

公开(公告)号：US11605710B2

公开(公告)日：2023-03-14

申请号：US17155469

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Uzma B. Rana ,  Anthony K. Stamper ,  Steven M. Shank ,  Srikanth Srihari

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/10

Abstract: A transistor includes a bulk semiconductor substrate, and a first source/drain region in the bulk semiconductor substrate separated from a second source/drain region in the bulk semiconductor substrate by a channel region. A first air gap is defined in the bulk semiconductor substrate under the first source/drain region, and a second air gap is defined in the bulk semiconductor substrate under the second source/drain region. A gate is over the channel region. A spacing between the first air gap and the second air gap is greater than or equal to a length of the channel region such that the first and second air gaps are not under the channel region. The air gaps may have a rectangular cross-sectional shape. The air gaps reduce off capacitance of the bulk semiconductor structure to near semiconductor-on-insulator levels without the disadvantages of an air gap under the channel region.

公开(公告)号：US11410872B2

公开(公告)日：2022-08-09

申请号：US16206375

申请日：2018-11-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L21/308 ,  H01L29/10 ,  H01L21/306 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to oxidized cavity structures within and under semiconductor devices and methods of manufacture. The structure includes: a substrate material; active devices over the substrate material; an oxidized trench structure extending into the substrate and surrounding the active devices; and one or more oxidized cavity structures extending from the oxidized trench structure and formed in the substrate material under the active devices.

公开(公告)号：US20220238631A1

公开(公告)日：2022-07-28

申请号：US17155445

申请日：2021-01-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Michael J. Zierak ,  Siva P. Adusumilli ,  Yves T. Ngu ,  Steven M. Shank

IPC: H01L49/02 ,  H01L21/762

Abstract: A structure provides a polysilicon resistor under a shallow trench isolation (STI). The structure includes the STI, a resistor in the form of a doped buried polysilicon layer under the STI, and a high resistivity (HR) polysilicon layer under the doped buried polysilicon layer. The structure also includes a pair of contacts operatively coupled in a spaced manner to the doped buried polysilicon layer. A related method is also disclosed.