公开(公告)号：US20080251948A1

公开(公告)日：2008-10-16

申请号：US12147929

申请日：2008-06-27

申请人： Geng-Shin Shen ,  David Wei Wang

发明人： Geng-Shin Shen ,  David Wei Wang

IPC分类号： H01L23/498

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83193 ,  H01L2224/83194 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A chip package structure including a first substrate, a second substrate, a plurality of bumps, a first B-staged adhesive layer and a second B-staged adhesive layer is provided. The first substrate has a plurality of first bonding pads. The second substrate has a plurality of second bonding pads, and the second substrate is disposed above the first substrate. The bumps are disposed between the first substrate and the second substrate, wherein each of the first bonding pads is respectively electrically connected to one of the second bonding pads via one of the bumps. The first B-staged adhesive layer is adhered on the first substrate. The second B-staged adhesive layer is adhered between the first B-staged adhesive layer and the second substrate, wherein the first B-staged adhesive layer and the second B-staged adhesive layer encapsulate the bumps.

摘要翻译： 提供了包括第一基板，第二基板，多个凸块，第一B阶粘合剂层和第二B阶粘合剂层的芯片封装结构。 第一基板具有多个第一接合焊盘。 第二基板具有多个第二接合焊盘，第二基板设置在第一基板的上方。 所述凸块设置在所述第一基板和所述第二基板之间，其中所述第一接合焊盘中的每一个分别经由所述凸块之一电连接到所述第二接合焊盘中的一个。 第一B级粘合剂层粘附在第一基底上。 第二B阶粘合剂层粘附在第一B阶粘合剂层和第二基底之间，其中第一B阶粘合剂层和第二B阶粘合剂层包封凸块。

公开(公告)号：US20080099896A1

公开(公告)日：2008-05-01

申请号：US11826516

申请日：2007-07-16

申请人： Geng-Shin Shen ,  Wu-Chang Tu

发明人： Geng-Shin Shen ,  Wu-Chang Tu

IPC分类号： H01L23/495

CPC分类号： H01L23/49541 ,  H01L23/49531 ,  H01L23/49551 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/10161 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： The present invention provides a stacked chip package structure with leadframe having inner leads with transfer pad, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and vertically distant from the plurality of inner leads; an offset chip-stacked structure formed with a plurality of chips stacked together, the offset chip-stacked structure being set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the offset chip-stacked structure and the leadframe, the plurality of outer leads extending out of said encapsulant; the improvement of which being that the inner leads of the leadframe are coated with an insulating layer and a plurality of metal pads are selectively formed on the insulating layer.

摘要翻译： 本发明提供一种具有引线框架的堆叠式芯片封装结构，其具有带有传输焊盘的内引线，包括：引线框架，由相互排列成行的多个内引线，多个外引线和管芯焊盘构成， 衬垫设置在彼此相对并且彼此垂直远离多个内引线的行中排列的多个内引线之间; 偏移芯片堆叠结构，其形成有堆叠在一起的多个芯片，所述偏移芯片堆叠结构设置在所述管芯焊盘上并电连接到彼此面对的行布置的所述多个内部引线; 以及覆盖所述偏移芯片堆叠结构和所述引线框的密封剂，所述多个外引线从所述密封剂延伸出来; 其改进之处在于引线框架的内引线被覆有绝缘层，并且绝缘层上选择性地形成多个金属焊盘。

公开(公告)号：US20080061412A1

公开(公告)日：2008-03-13

申请号：US11826413

申请日：2007-07-16

申请人： Geng-Shin Shen ,  Wu-Chang Tu

发明人： Geng-Shin Shen ,  Wu-Chang Tu

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L23/49531 ,  H01L23/49541 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/838 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/48145 ,  H01L2924/00

摘要： The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.

摘要翻译： 本发明提供了一种具有多片汇流条的引线框的芯片堆叠封装结构，包括：引线框架，由相互面对排列的多个内引线，多个外引线和管芯焊盘组成，其中， 芯片焊盘设置在彼此相对排列的多个内部引线之间，并且与多个内部引线垂直; 芯片堆叠结构，其形成有堆叠在一起并设置在芯片焊盘上的多个芯片，多个芯片和布置成彼此面对的多个内部引线彼此电连接; 以及提供以覆盖芯片堆叠结构和引线框架的密封剂; 其中，所述引线框架至少包括设置在彼此面对的所述多个内引线之间的汇流条和所述管芯焊盘，所述母线由多个部件形成。

公开(公告)号：US20070215992A1

公开(公告)日：2007-09-20

申请号：US11481719

申请日：2006-07-05

申请人： Geng-Shin Shen ,  Chun-Hung Lin

发明人： Geng-Shin Shen ,  Chun-Hung Lin

IPC分类号： H01L23/495

CPC分类号： H01L23/49575 ,  H01L21/563 ,  H01L21/6836 ,  H01L23/3107 ,  H01L23/4951 ,  H01L23/49513 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/0401 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/274 ,  H01L2224/29007 ,  H01L2224/29101 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83191 ,  H01L2224/83194 ,  H01L2224/83855 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A wafer treating method for making adhesive chips is provided. A liquid adhesive with two-stage property is coated on a surface of a wafer. Then, the wafer is pre-cured to make the liquid adhesive transform an adhesive film having B-stage property which has a glass transition temperature between −40 and 175 degree C. for example. After positioning the wafer, the wafer is singulated to form a plurality of chips with adhesive for chip-to-chip stacking, chip-to-substrate or chip-to-lead frame attaching.

摘要翻译： 提供了制造粘合剂芯片的晶片处理方法。 具有两级特性的液体粘合剂涂覆在晶片的表面上。 然后，将晶片预固化，以使液体粘合剂例如具有玻璃化转变温度在-40至175℃之间的具有B阶特性的粘合剂膜。 在晶片定位之后，晶片被单片化以形成具有用于芯片到芯片堆叠，芯片到衬底或芯片到引线框架连接的粘合剂的多个芯片。

公开(公告)号：US20070063325A1

公开(公告)日：2007-03-22

申请号：US11361646

申请日：2006-02-24

申请人： Chun-Hung Lin ,  Geng-Shin Shen

发明人： Chun-Hung Lin ,  Geng-Shin Shen

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/90 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/731 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

摘要： A chip package structure including a first substrate, a second substrate, bumps and adhesive blocks is provided. The first substrate has first bonding pads. The second substrate is disposed above the first substrate and has second bonding pads. The bumps are respectively arranged on the first bonding pads or the second bonding pads, and the second substrate is electrically connected to the first substrate through the bumps. The adhesive material with B-stage property are respectively arranged between the first bonding pads and the second bonding pads and enclose each bump. The bumps can be stud bumps or plating bumps.

摘要翻译： 提供了包括第一基板，第二基板，凸块和粘合块的芯片封装结构。 第一衬底具有第一接合焊盘。 第二基板设置在第一基板上方并具有第二接合焊盘。 凸块分别布置在第一接合焊盘或第二接合焊盘上，并且第二衬底通过凸块电连接到第一衬底。 具有B阶特性的粘合剂材料分别布置在第一接合焊盘和第二接合焊盘之间并且包围每个凸块。 凸块可以是凸块或电镀凸块。

公开(公告)号：US20070020816A1

公开(公告)日：2007-01-25

申请号：US11326749

申请日：2006-01-05

申请人： Yu-Tang Pan ,  Geng-Shin Shen ,  Chun-Hung Lin

发明人： Yu-Tang Pan ,  Geng-Shin Shen ,  Chun-Hung Lin

IPC分类号： H01L21/00

CPC分类号： H01L23/3128 ,  H01L21/4857 ,  H01L24/45 ,  H01L24/48 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/06136 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73204 ,  H01L2224/73215 ,  H01L2224/92147 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing process for chip package without core is disclosed. First of all, a conductive layer with a first surface and a second surface is provided. A first film is formed onto the first surface, and the conductive layer is patterned to form a patterned circuit layer. A solder resistance layer is formed on the patterned circuit layer and then patterned to expose parts of the patterned circuit layer. After a second film is formed on the solder resistance layer and the first film is removed, a chip is disposed on the first surface and electrically connected to the patterned circuit layer. A molding compound is formed to cover the patterned circuit layer and fix the chip onto the patterned circuit layer. After that, the second film is removed.

摘要翻译： 公开了一种无芯片封装的制造工艺。 首先，提供具有第一表面和第二表面的导电层。 第一膜形成在第一表面上，并且导电层被图案化以形成图案化的电路层。 在图案化电路层上形成阻焊层，然后将其图案化以暴露图案化电路层的部分。 在阻焊层上形成第二膜并且去除第一膜之后，在第一表面上设置芯片并与图案化电路层电连接。 形成模塑料以覆盖图案化电路层并将芯片固定在图案化电路层上。 之后，第二个膜被去除。