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    Silicon waveguide on bulk silicon substrate and methods of forming
    91.
    发明授权
    Silicon waveguide on bulk silicon substrate and methods of forming 有权
    体硅衬底上的硅波导及其形成方法

    公开(公告)号：US09385022B2

    公开(公告)日：2016-07-05

    申请号：US14283984

    申请日：2014-05-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Mark D. Jaffe ,  Alvin J. Joseph ,  Qizhi Liu ,  Anthony K. Stamper

    IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  G02B6/134 ,  G02B6/136 ,  G02B6/132 ,  G02B6/12 ,  G02B6/122

    CPC classification number: H01L21/76224 ,  G02B6/12004 ,  G02B6/122 ,  G02B6/132 ,  G02B6/1347 ,  G02B6/136 ,  G02B2006/12061 ,  H01L21/762 ,  H01L29/06 ,  H01L29/0649

    Abstract: Various methods include: forming an optical waveguide in a bulk silicon layer, the optical waveguide including a set of shallow trench isolation (STI) regions overlying a silicon substrate region; ion implanting the silicon substrate to amorphize a portion of the silicon substrate; forming a set of trenches through the STI regions and into the underlying silicon substrate region; undercut etching the silicon substrate region under the STI regions through the set of trenches to form a set of cavities, wherein the at least partially amorphized portion of the silicon substrate etches at a rate less than an etch rate of the silicon substrate; and sealing the set of cavities.

    Abstract translation: 各种方法包括：在体硅层中形成光波导，光波导包括覆盖硅衬底区域的一组浅沟槽隔离（STI）区域; 离子注入硅衬底以使硅衬底的一部分非晶化; 通过STI区域形成一组沟槽并进入下面的硅衬底区域; 底切蚀刻在STI区域下方的硅衬底区域通过该组沟槽以形成一组空穴，其中硅衬底的至少部分非晶化部分以小于硅衬底的蚀刻速率的速率蚀刻; 并密封该组腔。

    Methods for selective reverse mask planarization and interconnect structures formed thereby
    92.
    发明授权
    Methods for selective reverse mask planarization and interconnect structures formed thereby 有权
    用于选择性反向掩模平面化和由此形成的互连结构的方法

    公开(公告)号：US09269666B2

    公开(公告)日：2016-02-23

    申请号：US14158904

    申请日：2014-01-20

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

    IPC: H01L23/528 ,  H01L21/3105 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

    Abstract translation: 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。

    SOI wafers with buried dielectric layers to prevent CU diffusion
    98.
    发明授权
    SOI wafers with buried dielectric layers to prevent CU diffusion 有权

    公开(公告)号：US10242947B2

    公开(公告)日：2019-03-26

    申请号：US15713756

    申请日：2017-09-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Anthony K. Stamper ,  Mukta G. Farooq ,  John A. Fitzsimmons

    IPC: H01L21/76 ,  H01L23/532 ,  H01L21/762 ,  H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522

    Abstract: An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.

    Shallow trench isolation formation without planarization
    99.
    发明授权
    Shallow trench isolation formation without planarization 有权

    公开(公告)号：US10163679B1

    公开(公告)日：2018-12-25

    申请号：US15609742

    申请日：2017-05-31

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Richard A. Phelps ,  Anthony K. Stamper

    IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02

    Abstract: Structures for shallow trench isolation regions and methods for forming shallow trench isolation regions. A trench is etched partially through a device layer of a silicon-on-insulator substrate. A section of the device layer at a bottom of the trench is thermally oxidized to form a shallow trench isolation region in the trench. During the thermal oxidation, another region of the device layer may be concurrently oxidized over a partial thickness and, after removal of the oxide from this device layer region, used as a thinned silicon body. Prior to the thermal oxidation process, this device layer region may be implanted with an oxidation-retarding species that decreases its oxidation rate in comparison with the oxidation rate of the section of the device layer used to form the shallow trench isolation region.

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