公开(公告)号：US09390969B2

公开(公告)日：2016-07-12

申请号：US14600273

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： David A. DeMuynck ,  Zhong-Xiang He ,  Daniel R. Miga ,  Matthew D. Moon ,  Daniel S. Vanslette ,  Eric J. White

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L21/76843 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76879 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.

Abstract translation: 本公开一般涉及集成电路（IC），IC互连及其制造方法，更具体地，涉及高性能电感器。 IC包括设置在基板上的电介质层内的至少一个沟槽。 沟槽被保形地涂覆有衬里和种子层，并且包括内部的互连。 互连包括在互连的侧壁上的硬掩模。

公开(公告)号：US09708508B2

公开(公告)日：2017-07-18

申请号：US14733235

申请日：2015-06-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Graham M. Bates ,  Michael T. Brigham ,  Joseph K. Comeau ,  Jason P. Ritter ,  Matthew T. Tiersch ,  Eva A. Shah ,  Eric J. White

IPC: H01L21/461 ,  C09G1/04 ,  H01L21/321 ,  C09G1/02 ,  C09K3/14 ,  H01L21/768 ,  C11D11/00

CPC classification number: C09G1/04 ,  C09G1/02 ,  C09K3/1463 ,  C09K3/1472 ,  C11D11/0047 ,  H01L21/3212 ,  H01L21/7684

Abstract: A composition and a method for chemical mechanical polishing. The composition includes a surfactant anion an alkyl alcohol and a diluent. The composition further includes abrasive particles and an oxidizer. The method includes providing the composition on a surface to be polished and polishing the surface by contacting the surface with a polishing pad.

公开(公告)号：US09269666B2

公开(公告)日：2016-02-23

申请号：US14158904

申请日：2014-01-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Zhong-Xiang He ,  Anthony K. Stamper ,  Eric J. White

IPC: H01L23/528 ,  H01L21/3105 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/31056 ,  H01L21/76819 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for planarizing layers of a material, such as a dielectric, and interconnect structures formed by the planarization methods. The method includes depositing a first dielectric layer on a top surface of multiple conductive features and on a top surface of a substrate between the conductive features. A portion of the first dielectric layer is selectively removed from the top surface of at least one of the conductive features without removing a portion the first dielectric layer that is between the conductive features. A second dielectric layer is formed on the top surface of the at least one of the conductive features and on a top surface of the first dielectric layer, and a top surface of the second dielectric layer is planarized. A layer operating as an etch stop is located between the top surface of at least one of the conductive features and the second dielectric layer.

Abstract translation: 用于平坦化诸如电介质的材料层的平面化方法以及通过平面化方法形成的互连结构。 该方法包括在多个导电特征的顶表面和导电特征之间的衬底的顶表面上沉积第一介电层。 第一介电层的一部分从至少一个导电特征的顶表面选择性地去除，而不去除导电特征之间的第一介电层的一部分。 第二电介质层形成在至少一个导电特征的顶表面上和第一介电层的顶表面上，并且第二介电层的顶表面被平坦化。 作为蚀刻停止件操作的层位于导电特征中的至少一个的顶表面和第二介电层之间。