公开(公告)号：US06380067B1

公开(公告)日：2002-04-30

申请号：US09588119

申请日：2000-05-31

申请人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

发明人： Ramkumar Subramanian ,  Minh Van Ngo ,  Suzette K. Pangrle ,  Kashmir Sahota ,  Christopher F. Lyons

IPC分类号： H01L21302

CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/76802 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

摘要翻译： 本发明提供一种用于制造半导体器件的方法，该半导体器件具有用作蚀刻停止层并且不需要去除的底部抗反射涂层（BARC）。 在一个实施例中，电子器件形成在半导体衬底上。 然后为每个电气设备形成触点，然后沉积部分UV透明的BARC。 然后形成层间电介质（ILD）层，然后用光致抗蚀剂覆盖。 然后加入顶部ARC（TARC），然后对光致抗蚀剂进行光刻处理并随后显影。 然后将TARC，ILD和BARC层选择性地刻蚀成形成局部互连的器件触点。 光致抗蚀剂和TARC随后被去除，但由于其光学透明性，BARC不需要去除。

公开(公告)号：US06380047B1

公开(公告)日：2002-04-30

申请号：US09634990

申请日：2000-08-08

申请人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

发明人： Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Ibok ,  Christopher F. Lyons

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

摘要翻译： 使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料 沟渠 然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。 由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。 此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

公开(公告)号：US06358856B1

公开(公告)日：2002-03-19

申请号：US09716215

申请日：2000-11-21

申请人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

发明人： Christopher F. Lyons ,  Ramkumar Subramanian ,  Marina V. Plat ,  Todd P. Lukanc

IPC分类号： H01L21311

CPC分类号： H01L21/31144

摘要： A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.

摘要翻译： 形成小接触孔的方法使用亮场掩模在正抗蚀剂层中形成小圆筒。 在小圆筒周围形成负的抗蚀剂层，然后被蚀刻或抛光回去，使得暴露在负性抗蚀剂层上方的小圆筒的顶部部分留下。 负抗蚀剂层和小圆筒（正性抗蚀剂）暴露于光下，然后经受显影剂。 剩下的是一个位于小圆柱之前所在的小接触孔。

公开(公告)号：US06319802B1

公开(公告)日：2001-11-20

申请号：US09620145

申请日：2000-07-20

申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Bhanwar Singh ,  Marina Plat

发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Bhanwar Singh ,  Marina Plat

IPC分类号： H01L213205

CPC分类号： H01L21/28114

摘要： A method for fabricating a T-gate structure is provided. A structure is provided that has a silicon layer having a gate oxide layer, a protection layer over the gate oxide layer and a sacrificial layer over the protection layer. An opening is then formed in the sacrificial layer. A contact material is deposited over the sacrificial layer filling the opening with the contact material and forming a contact layer. Portions of the contact material outside a gate region are then removed. Finally, the sacrificial layer and portions of the protection layer and the gate oxide layer not forming a part of the T-gate structure are removed.

摘要翻译： 提供了一种制造T型栅结构的方法。 提供了一种具有硅层的结构，该硅层具有栅极氧化物层，栅极氧化物层上的保护层和保护层上的牺牲层。 然后在牺牲层中形成开口。 接触材料沉积在用接触材料填充开口的牺牲层上并形成接触层。 然后去除栅极区域外部的接触材料的部分。 最后，除去牺牲层和不形成T栅结构的一部分的保护层和栅极氧化物层的部分。

公开(公告)号：US06183938B2

公开(公告)日：2001-02-06

申请号：US09207551

申请日：1998-12-08

申请人： Christopher F. Lyons ,  Michael K. Templeton

发明人： Christopher F. Lyons ,  Michael K. Templeton

IPC分类号： G03F700

CPC分类号： H01L21/3088 ,  G03F7/00 ,  G03F7/0035 ,  G03F7/0045 ,  H01L21/0338

摘要： In one embodiment, the present invention relates to a method of making a sub-lithographic structure involving the steps of providing a nitrogen rich film over a portion of a substrate; depositing a photoresist over the nitrogen rich film and the substrate, wherein the photoresist and the nitrogen rich film interact and form a thin desensitized resist layer around an interface between the photoresist and the nitrogen rich film; exposing the photoresist to radiation; developing the photoresist exposing the thin desensitized resist layer; directionally etching a portion of the thin desensitized resist layer; and removing the nitrogen rich film leaving the sub-lithographic structure on the substrate.

摘要翻译： 在一个实施方案中，本发明涉及一种制备亚光刻结构的方法，其涉及以下步骤：在衬底的一部分上提供富氮膜; 在富氮膜和衬底上沉积光致抗蚀剂，其中光致抗蚀剂和富氮膜相互作用并在光致抗蚀剂和富氮膜之间的界面周围形成薄的脱敏抗蚀剂层; 将光致抗蚀剂暴露于辐射; 显影曝光薄的脱敏抗蚀剂层的光致抗蚀剂; 定向蚀刻一部分薄的脱敏抗蚀剂层; 并除去留在基板上的亚光刻结构的富氮膜。

公开(公告)号：US6124183A

公开(公告)日：2000-09-26

申请号：US992490

申请日：1997-12-18

申请人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

发明人： Olov Karlsson ,  Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Larry Wang ,  Effiong Ibok

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.

摘要翻译： 使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。 实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分 绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。 由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。 由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。

公开(公告)号：US6090712A

公开(公告)日：2000-07-18

申请号：US992489

申请日：1997-12-18

申请人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

发明人： Christopher F. Lyons ,  Basab Bandyopadhyay ,  Nick Kepler ,  Olov Karlsson ,  Larry Wang ,  Effiong Obok

IPC分类号： H01L21/762 ,  H01L21/461

CPC分类号： H01L21/76224

摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer while avoiding substrate damage, thereby simplifying trench formation and improving planarity. After trench fill, polishing is conducted to effect substantial planarization without exposing the substrate surface, thereby avoiding substrate damage. Etching is then conducted to expose the substrate surface. The omission of the barrier nitride polish stop avoids generation of a topographical step at the substrate/trench fill interface, thereby enhancing the accuracy of subsequent photolithographic techniques in forming features with minimal dimensions.

摘要翻译： 在半导体衬底中形成绝缘沟槽隔离结构，省略了阻挡氮化物抛光停止层，同时避免了衬底损坏，从而简化了沟槽形成并提高了平面度。 在沟槽填充之后，进行抛光以实现基本平坦化而不暴露衬底表面，从而避免衬底损坏。 然后进行蚀刻以暴露衬底表面。 阻挡氮化物抛光停止的省略避免了在衬底/沟槽填充界面处产生形貌步骤，从而在最小尺寸形成特征的同时提高随后的光刻技术的精度。

公开(公告)号：US07427457B1

公开(公告)日：2008-09-23

申请号：US10934277

申请日：2004-09-03

申请人： Marina V. Plat ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Anna M. Minvielle

发明人： Marina V. Plat ,  Calvin T. Gabriel ,  Christopher F. Lyons ,  Anna M. Minvielle

IPC分类号： G03F9/00

CPC分类号： G03F7/70783 ,  G03F1/44 ,  G03F7/70491 ,  G03F7/70533 ,  G03F7/7065

摘要： The present invention discloses a system and method for designing grating structures for use in situ scatterometry during the photolithography process to detect a photoresist defect (e.g., photoresist erosion, pattern collapse or pattern bending). In one embodiment, a grating structure may be designed with a pitch or critical dimensional smaller than the one used for the semiconductor device. The pitch and the critical dimension of the grating structure may be varied. In another embodiment, the present invention provides for a feedback mechanism between the in situ scatterometry process and the photolithography process to provide an early warning of the existence of a photoresist defect. If a defect is detected on the wafer, the wafer may be sent to be re-worked or re-patterned, thereby avoiding scrapping the entire wafer.

摘要翻译： 本发明公开了一种用于在光刻工艺期间用于原位散射测量的光栅结构的系统和方法，用于检测光致抗蚀剂缺陷（例如，光致抗蚀剂侵蚀，图案崩溃或图案弯曲）。 在一个实施例中，可以设计具有小于用于半导体器件的间距或临界尺寸的光栅结构。 光栅结构的间距和临界尺寸可以变化。 在另一个实施例中，本发明提供了原位散射测量过程和光刻工艺之间的反馈机制，以提供光刻胶缺陷的存在的早期警告。 如果在晶片上检测到缺陷，则可以将晶片发送以进行再加工或重新图案化，从而避免报废整个晶片。

公开(公告)号：US06852455B1

公开(公告)日：2005-02-08

申请号：US10237643

申请日：2002-09-09

申请人： Christopher F. Lyons ,  Cyrus E. Tabery

发明人： Christopher F. Lyons ,  Cyrus E. Tabery

IPC分类号： G03F1/00 ,  G03F1/08 ,  G03F9/00

CPC分类号： G03F1/32 ,  G03F1/54

摘要： An exemplary embodiment relates to a phase shifting mask including a glass substrate layer and an amorphous carbon absorber layer located above the glass substrate layer. The amorphous carbon absorber layer includes apertures through which light passes unaltered to the glass substrate layer.

摘要翻译： 示例性实施例涉及包括玻璃基底层和位于玻璃基底层上方的无定形碳吸收层的相移掩模。 无定形碳吸收层包括孔，光穿过该孔不改变到玻璃基底层。

公开(公告)号：US06803267B1

公开(公告)日：2004-10-12

申请号：US10614484

申请日：2003-07-07

申请人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

发明人： Ramkumar Subramanian ,  Christopher F. Lyons ,  Matthew S. Buynoski ,  Patrick K. Cheung ,  Angela T. Hui ,  Ashok M. Khathuria ,  Sergey D. Lopatin ,  Minh Van Ngo ,  Jane V. Oglesby ,  Terence C. Tong ,  James J. Xie

IPC分类号： H01L21336

CPC分类号： H01L27/28 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0018

摘要： The present invention provides a method to fabricate an organic memory device, wherein the fabrication method includes forming a lower electrode, depositing a passive material over the surface of the lower electrode, applying an organic semiconductor material over the passive material, and operatively coupling the an upper electrode to the lower electrode through the organic semiconductor material and the passive material. Patterning of the organic semiconductor material is achieved by depositing a silicon-based resist over the organic semiconductor, irradiating portions of the silicon-based resist and patterning the silicon-based resist to remove the irradiated portions of the silicon-based resist. Thereafter, the exposed organic semiconductor can be patterned, and the non-irradiated silicon-based resist can be stripped to expose the organic semiconductor material that can be employed as a memory cell for single and multi-cell memory devices. A partitioning component can be integrated with the memory device to facilitate stacking memory devices and programming, reading, writing and erasing memory elements.

摘要翻译： 本发明提供一种制造有机存储器件的方法，其中所述制造方法包括形成下电极，在所述下电极的表面上沉积无源材料，在所述被动材料上施加有机半导体材料，以及将所述有源半导体材料 上电极通过有机半导体材料和被动材料到下电极。 有机半导体材料的图案化是通过在有机半导体上沉积硅基抗蚀剂，照射硅基抗蚀剂的部分并图案化硅基抗蚀剂以除去硅基抗蚀剂的照射部分来实现的。 此后，可以对暴露的有机半导体进行构图，并且可以剥离未照射的硅基抗蚀剂以暴露可用作单电池和多电池存储器件的存储器单元的有机半导体材料。 分区组件可以与存储器件集成，以便于堆叠存储器件和编程，读取，写入和擦除存储器元件。