公开(公告)号：US09478597B2

公开(公告)日：2016-10-25

申请号：US12556593

申请日：2009-09-10

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Rihito Wada ,  Yoko Chiba

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Rihito Wada ,  Yoko Chiba

IPC分类号： H01L29/786 ,  H01L27/32 ,  H01L27/12 ,  H01L51/52

CPC分类号： H01L27/3276 ,  H01L27/1225 ,  H01L27/3262 ,  H01L29/7869 ,  H01L51/5221

摘要： A display device includes a pixel portion in which a pixel is arranged in a matrix, the pixel including an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen and having a channel protective layer over a semiconductor layer to be a channel formation region overlapping a gate electrode layer and a pixel electrode layer electrically connected to the inverted staggered thin film transistor. In the periphery of the pixel portion in this display device, a pad portion including a conductive layer made of the same material as the pixel electrode layer is provided. In addition, the conductive layer is electrically connected to a common electrode layer formed on a counter substrate.

摘要翻译： 显示装置包括其中像素以矩阵形式布置的像素部分，该像素包括具有不同量的氧并且具有通道保护层的至少两种氧化物半导体层的组合的反交错薄膜晶体管 半导体层作为与栅电极层重叠的沟道形成区域和与反交错薄膜晶体管电连接的像素电极层。 在该显示装置的像素部的周围，设置由与像素电极层相同的材料构成的导电层的焊盘部。 另外，导电层与形成在对置基板上的公共电极层电连接。

公开(公告)号：US08772773B2

公开(公告)日：2014-07-08

申请号：US12553122

申请日：2009-09-03

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L29/04 ,  H01L27/12 ,  H01L29/786

摘要： A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

公开(公告)号：US08634230B2

公开(公告)日：2014-01-21

申请号：US13348950

申请日：2012-01-12

申请人： Hideki Uochi

发明人： Hideki Uochi

IPC分类号： G11C11/34

CPC分类号： H01L27/1156 ,  G11C16/0425 ,  G11C16/26 ,  H01L21/28273 ,  H01L27/1225

摘要： Data is written in the following manner: potentials of first and second control gates of a transistor are set at a potential for making a storage gate of the transistor a conductor, a potential of data to be stored is supplied to the storage gate, and at least one of the potentials of the first and second control gates is set at a potential for making the storage gate an insulator. Data is read in the following manner: the potential of the second control gate is set at a potential for making the storage gate an insulator; a potential is supplied to a wiring connected to one of a source and a drain of the transistor; then, a potential for reading is supplied to the first control gate to detect a change in the potential of a bit line connected to the other of the source and the drain.

摘要翻译： 数据以如下方式写入：晶体管的第一和第二控制栅极的电位被设置为使晶体管的存储栅极成为导体的电位，将存储的数据的电位提供给存储门，并且在 将第一和第二控制栅极的电位中的至少一个设置为使存储栅极成为绝缘体的可能性。 数据以如下方式读取：第二控制栅极的电位被设定为使存储栅极成为绝缘体的可能性; 电位被提供给连接到晶体管的源极和漏极之一的布线; 然后，向第一控制栅极提供读取电位，以检测连接到源极和漏极中的另一个的位线的电位变化。

公开(公告)号：US08630127B2

公开(公告)日：2014-01-14

申请号：US13166029

申请日：2011-06-22

申请人： Hideki Uochi ,  Koichiro Kamata

发明人： Hideki Uochi ,  Koichiro Kamata

IPC分类号： G11C7/00

CPC分类号： G11C13/0007 ,  G11C11/404 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0078 ,  G11C2213/53 ,  H01L27/115 ,  H01L29/16 ,  H01L29/24 ,  H01L29/247 ,  H01L29/49

摘要： Disclosed is a semiconductor device having a memory cell which comprises a transistor having a control gate and a storage gate. The storage gate comprises an oxide semiconductor and is able to be a conductor and an insulator depending on the potential of the storage gate and the potential of the control gate. Data is written by setting the potential of the control gate to allow the storage gate to be a conductor, supplying a potential of data to be stored to the storage gate, and setting the potential of the control gate to allow the storage gate to be an insulator. Data is read by supplying a potential for reading to a read signal line connected to one of a source and a drain of the transistor and detecting the change in potential of a bit line connected to the other of the source and the drain.

摘要翻译： 公开了一种具有存储单元的半导体器件，该存储单元包括具有控制栅极和存储栅极的晶体管。 存储栅极包括氧化物半导体，并且能够根据存储栅极的电位和控制栅极的电位而成为导体和绝缘体。 通过设置控制栅极的电位来允许存储门为导体，向存储门提供要存储的数据的电位，以及设置控制门的电位以允许存储门为 绝缘子。 通过向连接到晶体管的源极和漏极中的一个的读取信号线提供读取电位并检测与源极和漏极中的另一个连接的位线的电位变化来读取数据。

公开(公告)号：US08619227B2

公开(公告)日：2013-12-31

申请号：US13442932

申请日：2012-04-10

申请人： Hajime Kimura ,  Hideki Uochi

发明人： Hajime Kimura ,  Hideki Uochi

IPC分类号： G02F1/1343 ,  G02F1/1335

CPC分类号： G02F1/134363 ,  G02F1/133345 ,  G02F1/133371 ,  G02F1/133553 ,  G02F1/133555 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2201/124

摘要： It is an object of the present invention to apply a sufficient electrical field to a liquid crystal material in a horizontal electrical field liquid crystal display device typified by an FFS type. In a horizontal electrical field liquid crystal display, an electrical field is applied to a liquid crystal material right above a common electrode and a pixel electrode using plural pairs of electrodes rather than one pair of electrodes. One pair of electrodes includes a comb-shaped common electrode and a comb-shaped pixel electrode. Another pair of electrodes includes a common electrode provided in a pixel portion and the comb-shaped pixel electrode.

摘要翻译： 本发明的目的是在以FFS为代表的水平电场液晶显示装置中向液晶材料施加足够的电场。 在水平电场液晶显示器中，使用多对电极而不是一对电极将电场施加在公共电极正上方的液晶材料和像素电极上。 一对电极包括梳状公共电极和梳状像素电极。 另一对电极包括设置在像素部分中的公共电极和梳形像素电极。

公开(公告)号：US08390044B2

公开(公告)日：2013-03-05

申请号：US12954338

申请日：2010-11-24

申请人： Daisuke Kawae ,  Hideki Uochi ,  Shunpei Yamazaki

发明人： Daisuke Kawae ,  Hideki Uochi ,  Shunpei Yamazaki

IPC分类号： H01L31/062

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L29/78606 ,  H01L29/78642 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78696

摘要： A non-linear element (such as a diode) which includes an oxide semiconductor and has a favorable rectification property is provided. In a transistor including an oxide semiconductor in which the hydrogen concentration is 5×1019/cm3 or lower, a work function φms of a source electrode in contact with the oxide semiconductor, a work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ

摘要翻译： 提供了包括氧化物半导体并且具有有利的整流特性的非线性元件（例如二极管）。 在包含氢浓度为5×1019 / cm3以下的氧化物半导体的晶体管中，与氧化物半导体接触的源电极的功函数＆amp; ms，接触的漏电极的功函数＆phd 与氧化物半导体相比，氧化物半导体的电子亲和力χ满足＆lt; ms＆nlE;χ＆phgr; md，并且漏电极和氧化物半导体之间的接触面积大于源电极和源电极之间的接触面积 氧化物半导体。 通过电连接晶体管中的栅电极和漏电极，可以实现具有良好整流特性的非线性元件。

公开(公告)号：US08334540B2

公开(公告)日：2012-12-18

申请号：US13173559

申请日：2011-06-30

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L29/04

CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

摘要： The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first wiring layer and a second wiring layer which are over the gate insulating film and whose end portions overlap with the gate electrode; and an oxide semiconductor layer which is over the gate electrode and in contact with the gate insulating film and the end portions of the first wiring layer and the second wiring layer. The gate electrode of the non-linear element and a scan line or a signal line is included in a wiring, the first or second wiring layer of the non-linear element is directly connected to the wiring so as to apply the potential of the gate electrode.

摘要翻译： 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 第一布线层和第二布线层，其在栅极绝缘膜上方并且其端部与栅电极重叠; 以及氧化物半导体层，其在所述栅电极的上方并与所述栅极绝缘膜和所述第一布线层和所述第二布线层的端部接触。 非线性元件的栅电极和扫描线或信号线包括在布线中，非线性元件的第一或第二布线层直接连接到布线，以施加栅极的电位 电极。

公开(公告)号：US6133620A

公开(公告)日：2000-10-17

申请号：US222730

申请日：1998-12-29

申请人： Hideki Uochi

发明人： Hideki Uochi

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L27/1214 ,  H01L21/28088 ,  H01L21/76838 ,  H01L21/76895 ,  H01L29/66757 ,  H01L29/78621

摘要： A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection containing aluminum as the principal component; and a sixth step of forming over the second layer interconnection, a film containing silicon nitride as the principal component thereof.

摘要翻译： 一种包括薄膜晶体管的半导体器件及其制造方法，该方法包括：形成岛状半导体层的第一步骤，覆盖该半导体层的栅极绝缘膜和包含含有 铝作为主要成分形成在栅极绝缘膜上; 通过使用栅电极作为掩模，以自对准的方式将杂质引入半导体层的第二步骤; 形成覆盖栅电极的层间电介质，在源极和漏极中的至少一个中形成接触孔的第三步骤; 在整个表面上形成第四步，以铝为主要成分的膜，然后通过阳极氧化含铝的膜作为主要成分形成阳极氧化膜; 蚀刻含有铝作为主要成分的膜和阳极氧化膜的第五步骤，从而形成以铝为主要成分的第二层互连; 以及在第二层互连上形成第六步骤，包含以氮化硅为主要成分的膜。

公开(公告)号：US09048320B2

公开(公告)日：2015-06-02

申请号：US12556695

申请日：2009-09-10

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： G02F1/1333 ,  G02F1/136 ,  H01L29/786 ,  H01L27/02 ,  H01L27/12

CPC分类号： H01L29/7869 ,  H01L27/0266 ,  H01L27/1225 ,  H01L27/124

摘要： A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅绝缘层上的栅电极重叠的第一氧化物半导体层，与沟道形成区重叠的沟道保护层 的第一氧化物半导体层，以及一对第一布线层和第二布线层，其端部与沟道保护层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US08941114B2

公开(公告)日：2015-01-27

申请号：US12553122

申请日：2009-09-03

申请人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

发明人： Shunpei Yamazaki ,  Kengo Akimoto ,  Shigeki Komori ,  Hideki Uochi ,  Tomoya Futamura ,  Takahiro Kasahara

IPC分类号： H01L29/04 ,  H01L27/12 ,  G02F1/1368 ,  H01L29/786 ,  G02F1/1362

CPC分类号： H01L27/1214 ,  G02F1/13624 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78693

摘要： A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

摘要翻译： 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，一对第一和第二布线层，其端部与栅极绝缘层上的栅电极重叠，并且其中 层叠第二氧化物半导体层和导电层，以及与至少栅电极重叠并与栅极绝缘层接触的第一氧化物半导体层，导电层的侧面部和顶面部的一部分，以及 在第一布线层和第二布线层中的第二氧化物半导体层的侧面部分。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。