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公开(公告)号：US20190393091A1
公开(公告)日：2019-12-26
申请号：US16428026
申请日：2019-05-31
发明人： Kangguo Cheng , Juntao Li , Heng Wu , Peng Xu
IPC分类号： H01L21/822 , H01L27/092 , H01L27/12 , H01L21/8238 , H01L21/84
摘要： A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.
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公开(公告)号：US10483382B1
公开(公告)日：2019-11-19
申请号：US16278693
申请日：2019-02-18
发明人： Kangguo Cheng , Peng Xu , Heng Wu , Zhenxing Bi
IPC分类号： H01L29/66 , H01L29/08 , H01L21/768 , H01L29/45 , H01L23/528 , H01L21/84 , H01L29/78
摘要： A tunnel field-effect transistor having source and drain contacts made from different electrically conductive materials enables independent optimization of contact resistance on the source and drain sides of the transistor. Dielectric caps on the gate electrode, source contact and drain contact made from different materials allow the selective removal of portions of the caps during gate, source and drain wiring. A wiring strap can be formed across the gate and drain to electrically connect two source contacts together. Multiple drain contacts or multiple gate electrodes may alternatively be electrically connected by wiring straps. Strap wiring facilitates placing transistors in closer proximity to increase the number of transistors for a given chip area.
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公开(公告)号：US20190296123A1
公开(公告)日：2019-09-26
申请号：US15934210
申请日：2018-03-23
发明人： Choonghyun Lee , Kangguo Cheng , Heng Wu , Peng Xu
IPC分类号： H01L29/66 , H01L29/51 , H01L29/06 , H01L21/764 , H01L21/02
摘要： A method is presented for reducing parasitic capacitance. The method includes forming multi-layer spacers between source/drain regions, forming a dielectric liner over the multi-layer spacers and the source/drain regions, forming gate structures adjacent the multi-layer spacers, forming a self-aligned contact cap over the gate structures, and removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions.
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公开(公告)号：US10410928B2
公开(公告)日：2019-09-10
申请号：US15824537
申请日：2017-11-28
发明人： Kangguo Cheng , Choonghyun Lee , Juntao Li , Heng Wu , Peng Xu
IPC分类号： H01L29/06 , H01L21/311 , H01L27/088 , H01L21/8234 , H01L21/762 , H01L29/78 , H01L29/66
摘要： In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.
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公开(公告)号：US10381262B2
公开(公告)日：2019-08-13
申请号：US15873279
申请日：2018-01-17
发明人： Kangguo Cheng , Zuoguang Liu , Sebastian Naczas , Heng Wu , Peng Xu
IPC分类号： H01L21/76 , H01L21/764 , H01L29/06 , H01L29/423 , H01L29/786 , H01L21/8234 , H01L27/088
摘要： A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.
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公开(公告)号：US10347731B2
公开(公告)日：2019-07-09
申请号：US16159673
申请日：2018-10-14
发明人： Zhenxing Bi , Kangguo Cheng , Heng Wu , Peng Xu
IPC分类号： H01L29/423 , H01L29/08 , H01L29/66 , H01L21/8234 , H01L29/06 , H01L29/78
摘要： A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.
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公开(公告)号：US20190206999A1
公开(公告)日：2019-07-04
申请号：US15861167
申请日：2018-01-03
发明人： Peng Xu , Kangguo Cheng , Juntao Li , Heng Wu
IPC分类号： H01L29/10 , H01L29/66 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L29/78 , H01L29/165 , H01L29/06
CPC分类号： H01L29/1054 , H01L21/02532 , H01L21/3065 , H01L21/308 , H01L21/76224 , H01L29/0653 , H01L29/165 , H01L29/66545 , H01L29/6681 , H01L29/7851
摘要： A method of a forming a plurality of semiconductor fin structures that includes forming a sacrificial gate structure on a hardmask overlying a channel region portion of the plurality of sacrificial fins of a first semiconductor material and forming source and drain regions on opposing sides of the channel region. The sacrificial gate structure and the sacrificial fin structure are removed. A second semiconductor material is formed in an opening provided by removing the sacrificial gate structure and the sacrificial fin structure. The second semiconductor material is etched selective to the hardmask to provide a plurality of second semiconductor material fin structures. A function gate structure is formed on the channel region.
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公开(公告)号：US10243061B1
公开(公告)日：2019-03-26
申请号：US15814376
申请日：2017-11-15
发明人： Kangguo Cheng , Juntao Li , Heng Wu , Peng Xu
IPC分类号： H01L21/336 , H01L29/66 , H01L29/06 , H01L29/40 , H01L29/78 , H01L29/423 , H01L23/31 , H01L23/29 , H01L21/02 , H01L21/311
摘要： Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
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公开(公告)号：US10229985B1
公开(公告)日：2019-03-12
申请号：US15830665
申请日：2017-12-04
发明人： Juntao Li , Kangguo Cheng , Peng Xu , Heng Wu
IPC分类号： H01L29/66 , H01L29/06 , H01L21/3105 , H01L21/311 , H01L29/78
摘要： A method of forming a semiconductor structure includes patterning two or more fins over a top surface of a bottom source/drain layer, the bottom source/drain layer disposed over a substrate. The method also includes forming bottom spacers disposed over the top surface of the bottom source/drain layer between the two or more fins, the bottom spacers having a uniform height on sidewalls of the two or more fins. The bottom spacers comprise dielectric regions disposed adjacent the sidewalls of the two or more fins and at least partially filling divots in the bottom source/drain regions, and liner regions disposed adjacent the dielectric regions. The two or more fins comprise channels for a vertical field-effect transistor (VFET) device.
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公开(公告)号：US20190058045A1
公开(公告)日：2019-02-21
申请号：US15803951
申请日：2017-11-06
发明人： Kangguo Cheng , Juntao Li , Heng Wu , Peng Xu
IPC分类号： H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L29/41791 , H01L21/823481 , H01L21/823821 , H01L29/66545 , H01L29/6681 , H01L2029/7858
摘要： Embodiments of the invention are directed to methods of forming a FinFET. A non-limiting example method includes forming a fin across from a major surface of a substrate. A dummy gate is formed around a channel region of the fin. A source region or a drain region is formed on the fin, and the dummy gate is replaced with a metal gate structure. Subsequent to replacing the dummy gate with the metal gate structure, dopants are inserted into the source region or the drain region.
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