公开(公告)号：US10811322B1

公开(公告)日：2020-10-20

申请号：US16379950

申请日：2019-04-10

Applicant: International Business Machines Corporation

Inventor： Heng Wu ,  Kangguo Cheng ,  Chen Zhang ,  Tenko Yamashita

IPC: H01L21/8238 ,  H01L29/78 ,  H01L21/265 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L21/266

Abstract: A method of forming a semiconductor structure includes forming vertical fins comprising a first semiconductor layer, an isolation layer and a second semiconductor layer, the first and second semiconductor layers providing vertical transport channels for lower and upper vertical transport field-effect transistors (VTFETs) of a stacked VTFET structure. The method also includes forming a first gate stack for the lower VTFET surrounding a first portion of the first semiconductor layer of the vertical fins. The method further includes forming a second gate stack for the upper VTFET surrounding a second portion of the second semiconductor layer of the vertical fins. The first and second portions have different sizes such that the upper and lower VTFETs of the stacked VTFET structure have different effective gate widths.

公开(公告)号：US10804368B2

公开(公告)日：2020-10-13

申请号：US16049403

申请日：2018-07-30

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Junli Wang ,  Dechao Guo ,  Heng Wu ,  Ernest Y. Wu

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

Abstract: Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

公开(公告)号：US10573561B2

公开(公告)日：2020-02-25

申请号：US16428026

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/822 ,  H01L27/092 ,  H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.

公开(公告)号：US20200035808A1

公开(公告)日：2020-01-30

申请号：US16049403

申请日：2018-07-30

Applicant: International Business Machines Corporation

Inventor： Ruqiang Bao ,  Junli Wang ,  Dechao Guo ,  Heng Wu ,  Ernest Y. Wu

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66

Abstract: Techniques for fabricating a semiconductor device having a two-part spacer. In one embodiment, a device is provided that comprises a spacer having a first portion and a second portion, where the first portion comprises one or more layers and the second portion comprises a dielectric material. In one or more implementations, the device further comprises an isolation layer coupled to the spacer, where the isolation layer comprises a silicon oxide material. In one or implementation, the device can further comprise a gate structure formed on a substrate, where the gate structure comprises a polysilicon contact portion, a first silicon dioxide portion, a silicon nitride portion and a second silicon dioxide portion.

公开(公告)号：US20190393091A1

公开(公告)日：2019-12-26

申请号：US16428026

申请日：2019-05-31

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L21/822 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84

Abstract: A method of fabricating a stacked semiconductor device includes forming nanosheet stacks including silicon layers and silicon germanium layers on a substrate. The method includes growing a first epitaxial layer on a source and drain and depositing an interlayer dielectric on the first epitaxial layer. The method includes etching the interlayer dielectric to expose the first epitaxial layer. The method includes etching a portion of the first epitaxial layer and growing a second epitaxial layer on the first epitaxial layer and etching the interlayer dielectric and depositing a first liner in a recess left by the etching, forming a pFET. The method includes etching a portion of the first liner and removing the second epitaxial layer leaving a portion of the first epitaxial layer exposed and depositing a second insulator layer on the first epitaxial layer, forming an nFET. The pFET and nFET are disposed adjacent to one another vertically.

公开(公告)号：US10483382B1

公开(公告)日：2019-11-19

申请号：US16278693

申请日：2019-02-18

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Peng Xu ,  Heng Wu ,  Zhenxing Bi

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/768 ,  H01L29/45 ,  H01L23/528 ,  H01L21/84 ,  H01L29/78

Abstract: A tunnel field-effect transistor having source and drain contacts made from different electrically conductive materials enables independent optimization of contact resistance on the source and drain sides of the transistor. Dielectric caps on the gate electrode, source contact and drain contact made from different materials allow the selective removal of portions of the caps during gate, source and drain wiring. A wiring strap can be formed across the gate and drain to electrically connect two source contacts together. Multiple drain contacts or multiple gate electrodes may alternatively be electrically connected by wiring straps. Strap wiring facilitates placing transistors in closer proximity to increase the number of transistors for a given chip area.

公开(公告)号：US20190296123A1

公开(公告)日：2019-09-26

申请号：US15934210

申请日：2018-03-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Choonghyun Lee ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/06 ,  H01L21/764 ,  H01L21/02

Abstract: A method is presented for reducing parasitic capacitance. The method includes forming multi-layer spacers between source/drain regions, forming a dielectric liner over the multi-layer spacers and the source/drain regions, forming gate structures adjacent the multi-layer spacers, forming a self-aligned contact cap over the gate structures, and removing a sacrificial layer of each of the multi-layer spacers to form air-gaps between the gate structures and the source/drain regions.

公开(公告)号：US10410928B2

公开(公告)日：2019-09-10

申请号：US15824537

申请日：2017-11-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Choonghyun Lee ,  Juntao Li ,  Heng Wu ,  Peng Xu

IPC: H01L29/06 ,  H01L21/311 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66

Abstract: In accordance with an embodiment of the present invention, a method of forming a densified fill layer is provided. The method includes forming a pair of adjacent vertical fins on a substrate, forming an inner liner on the sidewalls of the adjacent vertical fins, and forming a sacrificial layer on the inner liner. The method further includes forming a fill layer between the pair of adjacent vertical fins, wherein the fill layer is in contact with at least a portion of the sacrificial layer, removing at least a portion of the sacrificial layer in contact with the fill layer to form sidewall channels adjacent to the fill layer, and subjecting the fill layer to a densification process to form the densified fill layer.

公开(公告)号：US10381262B2

公开(公告)日：2019-08-13

申请号：US15873279

申请日：2018-01-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Zuoguang Liu ,  Sebastian Naczas ,  Heng Wu ,  Peng Xu

IPC: H01L21/76 ,  H01L21/764 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234 ,  H01L27/088

Abstract: A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, including, forming a bottom source/drain region on a substrate, forming at least two vertical fins on the bottom source/drain region, forming a protective spacer on the at least two vertical fins, forming a sacrificial liner on the protective spacer, forming an isolation channel in the bottom source/drain region and substrate between two of the at least two vertical fins, forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel, and forming the dielectric separator on the insulating plug.

公开(公告)号：US10347731B2

公开(公告)日：2019-07-09

申请号：US16159673

申请日：2018-10-14

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Kangguo Cheng ,  Heng Wu ,  Peng Xu

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A field-effect transistor device including an asymmetric spacer assembly allows lower parasitic capacitance on the drain side of the device and lower resistance on the source side. The asymmetric spacer assembly is formed by a self-aligned process, resulting in less gate/junction overlap on the drain side of the device and greater gate/junction overlap on the source side of the device. Asymmetric transistors having small gate lengths can be obtained without overlay/misalignment issues.