公开(公告)号：US20210375873A1

公开(公告)日：2021-12-02

申请号：US16888910

申请日：2020-06-01

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek A. Sharma ,  Charles Kuo ,  Brian S. Doyle ,  Urusa Shahriar Alaan ,  Van H. Le ,  Elijah V. Karpov ,  Kaan Oguz ,  Arnab Sen Gupta

IPC: H01L27/108 ,  H01L25/065

Abstract: Embodiments may relate to a microelectronic package that includes a first plurality of memory cells of a first type coupled with a substrate. The microelectronic package may further include a second plurality of memory cells of a second type communicatively coupled with the substrate such that the first plurality of memory cells is between the substrate and the second plurality of memory cells. Other embodiments may be described or claimed.

公开(公告)号：US11114471B2

公开(公告)日：2021-09-07

申请号：US16633559

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Abhishek A. Sharma ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: H01L27/00 ,  H01L29/00 ,  H01L21/00 ,  H01L27/12 ,  H01L21/027 ,  H01L21/768 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/786

Abstract: Thin film transistors having relatively increased width and shared bitlines are described. In an example, an integrated circuit structure includes a plurality of transistors formed in an insulator structure above a substrate. The plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width. A first conductive contact is formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.

公开(公告)号：US10811336B2

公开(公告)日：2020-10-20

申请号：US15966577

申请日：2018-04-30

Applicant: INTEL CORPORATION

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Elijah V. Karpov ,  Prashant Majhi ,  Brian S. Doyle

IPC: H01L23/38 ,  H01L27/24 ,  H01L23/34 ,  H01L27/16 ,  H01L45/00 ,  H01L35/30 ,  H01L35/16 ,  H01L35/18 ,  H01L43/02 ,  H01L27/22

Abstract: Electronic devices, memory devices, and computing devices are disclosed. An electronic device includes electronic circuitry, a temperature sensor, a heat sink, at least one thermoelectric material, a thermally conductive material configured to thermally couple the electronic circuitry to the at least one thermoelectric material, and a transistor. The temperature sensor is configured to monitor a temperature of the electronic circuitry. The transistor is configured to selectively enable thermoelectric current to flow through the at least one thermoelectric material and dissipate heat from the thermally conductive material to the heat sink responsive to fluctuations in the temperature of the electronic circuitry detected by the temperature sensor.

公开(公告)号：US20200176457A1

公开(公告)日：2020-06-04

申请号：US16640467

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: H01L27/1159 ,  H01L29/51 ,  G11C11/22 ,  H01L29/78

Abstract: A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.

公开(公告)号：US20200098926A1

公开(公告)日：2020-03-26

申请号：US16142940

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  Prashant Majhi ,  Gilbert W. Dewey ,  Benjamin Chu-Kung ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/51 ,  H01L27/11585

Abstract: Disclosed herein are transistors with ferroelectric gates, and related methods and devices. For example, in some embodiments, a transistor may include a channel material, and a gate stack, and the gate stack may include a gate electrode material and a ferroelectric material between the gate electrode material and the channel material.

公开(公告)号：US20200051724A1

公开(公告)日：2020-02-13

申请号：US15735622

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Brian S. Doyle ,  Kaan Oguz ,  Kevin P. O'Brien ,  David L. Kencke ,  Charles C. Kuo ,  Mark L. Doczy ,  Satyarth Suri ,  Robert S. Chau

IPC: H01F10/193 ,  H01F10/32 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An embodiment includes an apparatus comprising: a substrate; a magnetic tunnel junction (MTJ), on the substrate, comprising a fixed layer, a free layer, and a dielectric layer between the fixed and free layers; and a first synthetic anti-ferromagnetic (SAF) layer, a second SAF layer, and an intermediate layer, which includes a non-magnetic metal, between the first and second SAF layers; wherein the first SAF layer includes a Heusler alloy. Other embodiments are described herein.

公开(公告)号：US10559744B2

公开(公告)日：2020-02-11

申请号：US16072301

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Brian Maertz ,  Christopher J. Wiegand ,  Daniel G. Oeullette ,  Md Tofizur Rahman ,  Oleg Golonzka ,  Justin S. Brockman ,  Tahir Ghani ,  Brian S. Doyle ,  Kevin P. O'Brien ,  Mark L. Doczy ,  Kaan Oguz

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

公开(公告)号：US10522739B2

公开(公告)日：2019-12-31

申请号：US15735616

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kaan Oguz ,  Kevin P. O'Brien ,  Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Robert S. Chau

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

Abstract: An embodiment includes an apparatus comprising: a substrate; and a perpendicular magnetic tunnel junction (pMTJ) comprising a fixed layer and first and second free layers; wherein (a) the first free layer includes Cobalt (Co), Iron (Fe), and Boron (B), and (b) the second free layer is epitaxial and includes Manganese (Mn) and Gallium (Ga). Other embodiments are described herein.

公开(公告)号：US20190385677A1

公开(公告)日：2019-12-19

申请号：US16011512

申请日：2018-06-18

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Elijah V. Karpov ,  Abhishek A. Sharma ,  Prashant Majhi ,  Brian S. Doyle

IPC: G11C13/00 ,  H01L45/00 ,  H01L29/786 ,  H01L29/423 ,  H01L27/24

Abstract: Described is a memory cell which comprises: a transistor positioned in a backend of a die, the transistor comprising: a source structure and a drain structure; a gate structure between the source structure and the drain structure; a source contact coupled to and above the source structure and a drain contact coupled to and below the drain structure; and a Resistive Random Access Memory (RRAM) device coupled to the drain contact.

公开(公告)号：US20190305045A1

公开(公告)日：2019-10-03

申请号：US15942115

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Brian S. Doyle ,  Ravi Pillarisetty ,  Prashant Majhi ,  Elijah V. Karpov

IPC: H01L27/24 ,  H01L27/108 ,  H01L27/22 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78 ,  H01L43/12 ,  H01L45/00 ,  H01L29/66 ,  H01L43/08

Abstract: An integrated circuit structure includes: a field-effect transistor including a semiconductor region including a semiconductor material having a bandgap less than or equal to that of silicon, a semiconductor source and a semiconductor drain, the semiconductor region being between the semiconductor source and the semiconductor drain, a gate electrode, a gate dielectric between the semiconductor region and the gate electrode, a source contact adjacent to the semiconductor source, and a drain contact adjacent to the semiconductor drain; and a resistive switch or a capacitor electrically connected to the drain contact. One of the source contact and the drain contact includes a threshold switching region, to be a selector for the resistive switch or the capacitor. In some embodiments, the threshold switching region includes a threshold switching oxide or a threshold switching chalcogenide, and the resistive switch or the capacitor is part of a resistive memory cell or capacitive memory cell.