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公开(公告)号：US09043604B2
公开(公告)日：2015-05-26
申请号：US13987807
申请日：2013-09-05
Applicant: Intel Corporation
Inventor： Ernest F. Brickell , Shay Gueron , Jiangtao Li , Carlos V. Rozas , Daniel Nemiroff , Vincent R. Scarlata , Uday R. Savagaonkar , Simon P. Johnson
CPC classification number: H04L9/0816 , G06F21/572 , G06F21/73
Abstract: Keying materials used for providing security in a platform are securely provisioned both online and offline to devices in a remote platform. The secure provisioning of the keying materials is based on a revision of firmware installed in the platform.
Abstract translation: 用于在平台中提供安全性的键控材料可以安全地在线和离线地配置到远程平台中的设备。 密钥材料的安全配置基于安装在平台中的固件的修订版本。
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公开(公告)号：US20150104010A1
公开(公告)日：2015-04-16
申请号：US14572607
申请日：2014-12-16
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150100797A1
公开(公告)日：2015-04-09
申请号：US14572578
申请日：2014-12-16
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US20150100796A1
公开(公告)日：2015-04-09
申请号：US14572423
申请日：2014-12-16
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal , Raghunandan Makaram , Martin G. Dixon , Srinivas Chennupaty , Michael E. Kounavis
CPC classification number: H04L9/0631 , G06F3/0623 , G06F3/0665 , G06F3/0689 , G06F9/30007 , G06F9/30036 , G06F9/30047 , G06F9/30145 , G06F9/30178 , G06F9/3802 , G06F9/3818 , G06F9/3887 , G06F9/3895 , G06F12/0862 , G06F12/0875 , G06F12/1408 , G06F21/602 , G06F2212/1052 , G06F2212/402 , G06F2212/452 , G06F2212/454 , G06F2212/602 , G11C7/1072 , H04L9/0816 , H04L9/0861 , H04L2209/12 , H04L2209/24
Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.
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公开(公告)号：US11687681B2
公开(公告)日：2023-06-27
申请号：US17020486
申请日：2020-09-14
Applicant: Intel Corporation
Inventor： Shay Gueron , Siddhartha Chhabra , Nadav Bonen
CPC classification number: G06F21/79 , G06F12/14 , G06F21/75 , G06F21/76 , G06F21/6218
Abstract: System and techniques for multi-tenant cryptographic memory isolation are described herein. A multiple key total memory encryption (MKTME) circuitry may receive a read request for encrypted memory. Here, the read request may include an encrypted memory address that itself includes a sequence of keyid bits and physical address bits. The MKTME circuitry may retrieve a keyid-nonce from a key table using the keyid bits. The MKTME circuitry may construct a tweak from the keyid-nonce, the keyid bits, and the physical address bits. The MKTME circuitry may then decrypt data specified by the read request using the tweak and a common key.
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Patent Agency Ranking
公开(公告)号：US11563556B2
公开(公告)日：2023-01-24
申请号：US16841241
申请日：2020-04-06
Applicant: Intel Corporation
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
Abstract: A processor of an aspect is to perform a Single Instruction Multiple Data (SIMD) instruction. The SIMD instruction is to indicate a source register storing input data to be processed by a round of AES and is to indicate a source of a round key to be used for the round of AES. The processor is to perform the SIMD instruction to perform the round of AES on the input data using the round key and store a result of the round of AES in a destination. In one aspect, the SIMD instruction is to provide a parameter to specify whether or not a round of AES to be performed is a last round. Other instructions, processors, methods, and systems are described.
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公开(公告)号：US11085964B2
公开(公告)日：2021-08-10
申请号：US16403296
申请日：2019-05-03
Applicant: Intel Corporation
Inventor： Tsvika Kurts , Boris Dolgunov , Vladislav Mladentsev , Ittai Anati , Elias Khoury , Maor Kima , Eran Shlomo , Shay Gueron , William Penner
IPC: G01R31/317 , G06F16/22 , G01R31/3177 , G06F11/263 , H04L9/06 , H04L9/08 , H04L9/32
Abstract: Systems and techniques of the present disclosure may provide remote debugging of an integrated circuit (IC) device while preventing unauthorized access of device intellectual property (IP). A system may include an IC device that generates an encrypted session key and an interface that enables communication between the IC device and a remote debugging site. The interface may enable the IC device to send the encrypted the encrypted session key to initiate a remote debug process, receive an acknowledgement from the remote debugging session, and authenticate the acknowledgement. Further, the interface may enable to the IC device to initiate a secure debug session between the IC device and the remote debugging site.
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公开(公告)号：US10601583B2
公开(公告)日：2020-03-24
申请号：US15639991
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
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公开(公告)号：US10594474B2
公开(公告)日：2020-03-17
申请号：US15639974
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
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公开(公告)号：US10587395B2
公开(公告)日：2020-03-10
申请号：US15639946
申请日：2017-06-30
Applicant: INTEL CORPORATION
Inventor： Shay Gueron , Wajdi K. Feghali , Vinodh Gopal
Abstract: A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
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