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公开(公告)号：US20090213522A1
公开(公告)日：2009-08-27
申请号：US12437575
申请日：2009-05-08
IPC分类号： H01G7/00
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译： 一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。 这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。 该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。 它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。
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公开(公告)号：US07579644B2
公开(公告)日：2009-08-25
申请号：US11436249
申请日：2006-05-18
IPC分类号： H01L29/94
CPC分类号： H01L27/0805 , H01L23/5223 , H01L27/0688 , H01L27/0808 , H01L2924/0002 , H01L2924/00
摘要： One or more on-chip VNCAP or MIMCAP capacitors utilize a variable MOS capacitor to improve the uniform capacitance value of the capacitors. This permits the production of silicon semiconductor chips on which are mounted capacitors having capacitive values that are precisely adjusted to be within a range of between about 1% and 5% of their design value. This optimization can be achieved by the use of a back-to-back connection between a pair of the variable MOS capacitors for DC decoupling. It involves the parallelization of on-chip BEOL capacitance of VNCAP and/or MIMCAP capacitors by the insertion in the FEOL of pairs of back-to-back variable MOS capacitors.
摘要翻译： 一个或多个片上VNCAP或MIMCAP电容器利用可变MOS电容来改善电容器的均匀电容值。 这允许生产硅半导体芯片，其上安装有具有精确调节的电容值的电容器在其设计值的约1％至5％的范围内。 该优化可以通过使用一对用于DC去耦的可变MOS电容器之间的背对背连接来实现。 它涉及VOCAP和/或MIMCAP电容器的片上BEOL电容的并联，通过在FEOL中插入成对的背对背可变MOS电容器。
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93.发明申请APPARATUS AND METHOD FOR RECYCLING AND REUSING CHARGE IN AN ELECTRONIC CIRCUIT 有权用于在电子电路中回收和重新充电的装置和方法公开(公告)号：US20090134844A1
公开(公告)日：2009-05-28
申请号：US11946550
申请日：2007-11-28
申请人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Choongyeun Cho , Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： H02J7/00
CPC分类号： H02J7/345
摘要： An apparatus and method for recycling and reusing charge in an electronic circuit. The apparatus includes at least one capacitor coupled to a circuit block in the electronic circuit, the capacitor being configured to collect current charge consumed by the circuit block when set to a charge collection mode, and a voltage level comparator configured to detect a fully charged state when the capacitor is fully charged. Further, the apparatus includes a first electrical switch configured to allow, once the fully charged state is detected, the capacitor to switch to a discharge mode for discharging the current charge collected back into the power supply for reuse by the electrical system and a second switch configured to allow, after the capacitor has fully discharged the current charge collected, the capacitor to switch back to the charge collection mode, such that, the current charge is recycled and reused by the electrical system.
摘要翻译： 一种用于在电子电路中再循环和再利用电荷的装置和方法。 该装置包括耦合到电子电路中的电路块的至少一个电容器，电容器被配置为当设置为电荷收集模式时收集由电路块消耗的当前电荷;以及电压电平比较器，被配置为检测完全充电状态 当电容器充满电时。 此外，该装置包括第一电开关，其被配置为允许一旦检测到完全充电状态，电容器切换到放电模式，用于将收集的当前电荷放回电源供电系统和第二开关 配置为允许在电容器已经完全放电所收集的当前电荷之后，电容器切换回电荷收集模式，使得当前电荷被电气系统再循环和再利用。
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公开(公告)号：US07418368B2
公开(公告)日：2008-08-26
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J Kim , James R Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译： 提供了系统，方法和程序代码，用于测试多核处理器芯片结构。 单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。 在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。 核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。
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公开(公告)号：US20080178023A1
公开(公告)日：2008-07-24
申请号：US11624333
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： Systems, methods and program codes are provided for selectively adjusting multi-core processor chip structure individual processor core power supply voltages through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. Nominal power supply voltage is supplied to a first processing core, and a second core power supply voltage greater or lower than the nominal power supply voltage is supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. The second power supply voltage may be selected from ordered discrete supply voltages derived by progressively lowering the nominal supply voltage, optionally wherein the selected supply voltage also enables the second core to operate within another performance specification.
摘要翻译： 提供了系统，方法和程序代码，用于通过控制每个核心的单个电源来选择性地调整多核处理器核心电源电压的多核处理器芯片结构，以确保一个或多个内核按照一个时钟速率运行 或更多性能规格。 标称电源电压被提供给第一处理核心，并且大于或低于标称电源电压的第二核心电源电压被提供给第二处理核心，两个核心都遵守参考时钟速率规范。 第二电源电压可以从通过逐渐降低标称电源电压而导出的有序的离散电源电压中选择，可选地，其中所选择的电源电压还使得第二磁芯能够在另一性能规范内操作。
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公开(公告)号：US20080099880A1
公开(公告)日：2008-05-01
申请号：US11970665
申请日：2008-01-08
CPC分类号： H01L29/94 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： Methods, articles and design structures for capacitance circuits are provided disposing a lower vertical-native capacitor metal layer above a planar front-end-of-line semiconductor base substrate, planar metal bottom plates spaced a bottom plate distance from the base and top plates above the bottom plates spaced a top plate distance from the base defining metal-insulator-metal capacitors, top plate footprints disposed above the base substrate smaller than bottom plate footprints and exposing bottom plate remainder upper lateral connector surfaces; disposing parallel positive port and negative port upper vertical-native capacitor metal layers over and each connected to top plate and bottom plate upper remainder lateral connector surface. Moreover, electrical connecting of the first top plate and the second bottom plate to the positive port metal layer and of the second top plate and the first bottom to the negative port metal layer impart equal total negative port and positive port metal-insulator-metal capacitor extrinsic capacitance.
摘要翻译： 提供了用于电容电路的方法，制品和设计结构，其在平面前端半导体基底基板上方设置较低的垂直电容器金属层，平板金属底板与底座和顶板间隔开底板 底板与限定金属 - 绝缘体 - 金属电容器的基板间隔开顶板距离，顶板脚印设置在基底基板之上，小于底板印迹，并露出底板剩余的上横向连接器表面; 将平行的正端口和负端口上垂直电容器金属层布置在每个顶板和底板的上部剩余侧面连接器表面上。 此外，第一顶板和第二底板与正端口金属层以及第二顶板和第一底部到负极金属层的电连接赋予相等的总负端口和正端口金属 - 绝缘体 - 金属电容器 外在电容。
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公开(公告)号：US09268720B2
公开(公告)日：2016-02-23
申请号：US12872282
申请日：2010-08-31
申请人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
发明人： Feng Wang , Shiqun Gu , Jonghae Kim , Matthew Michael Nowak
CPC分类号： G06F13/1647 , G06F12/0607 , G06F13/1642 , G06F13/1657 , G06F2213/0064
摘要： A load balancing in a multiple DRAM system comprises interleaving memory data across two or more memory channels. Access to the memory channels is controlled by memory controllers. Bus masters are coupled to the memory controllers via an interconnect system and memory requests are transmitted from the bus masters to the memory controller. If congestion is detected in a memory channel, congestion signals are generated and transmitted to the bus masters. Memory requests are accordingly withdrawn or rerouted to less congested memory channels based on the congestion signals.
摘要翻译： 多个DRAM系统中的负载平衡包括跨两个或多个存储器通道交织存储器数据。 内存通道的访问由内存控制器控制。 总线主机通过互连系统耦合到存储器控制器，并且存储器请求从总线主机传送到存储器控制器。 如果在存储器通道中检测到拥塞，则产生拥塞信号并将其发送到总线主机。 因此，基于拥塞信号，存储器请求被相应地撤回或重新路由到较不拥塞的存储器通道。
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98.发明授权Multi-frequency reconfigurable voltage controlled oscillator (VCO) and method of providing same 有权多频可重构压控振荡器（VCO）及其提供方法公开(公告)号：US09130505B2
公开(公告)日：2015-09-08
申请号：US13293361
申请日：2011-11-10
申请人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
发明人： Chengjie Zuo , Changhan Yun , Chi Shun Lo , Jonghae Kim
CPC分类号： H03B5/1243 , H03B5/1262 , H03B5/30 , H03B5/368 , H03B2200/0048 , H03B2201/0208 , Y10T29/49117
摘要： A multiple frequency reconfigurable voltage controlled oscillator (VCO) (136) includes a variable capacitance device (112), an inductor (116) coupled in parallel with the variable capacitance device (112), and at least two circuit paths (118, 120, 122) coupled in parallel with the variable capacitance device (112) and the inductor (116). The circuit paths (118, 120, 122) each include a piezoelectric laterally vibrating resonator (126, 130, 134) and a switch (124, 128, 132) for selectably coupling each piezoelectric laterally vibrating resonator (126, 130, 134) in parallel with the inductor (116) and variable capacitance device (112).
摘要翻译： 多频可重构压控振荡器（VCO）（136）包括可变电容装置（112），与可变电容装置（112）并联耦合的电感器（116）和至少两个电路路径（118,120， 122）与可变电容器件（112）和电感器（116）并联耦合。 电路路径（118,120,122）各自包括压电横向振动谐振器（126,130,134）和开关（124,128,132），用于将每个压电横向振动谐振器（126,130,134）可选地耦合在 与电感器（116）和可变电容器件（112）平行。
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公开(公告)号：US09001031B2
公开(公告)日：2015-04-07
申请号：US13562168
申请日：2012-07-30
申请人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
发明人： Chi Shun Lo , Je-Hsiung Jeffrey Lan , Mario Francisco Velez , Robert Paul Mikulka , Chengjie Zuo , Changhan Hobie Yun , Jonghae Kim
CPC分类号： H01F17/0006 , G02B26/001 , H01F27/2804 , H01L23/5227 , H01L28/10 , H01L2924/00 , H01L2924/0002
摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.
摘要翻译： 本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。 一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。
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公开(公告)号：US08627021B2
公开(公告)日：2014-01-07
申请号：US13222399
申请日：2011-08-31
申请人： Feng Wang , Jonghae Kim
发明人： Feng Wang , Jonghae Kim
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1652 , Y02D10/14
摘要： A load state of a slave memory is detected and provided to a master device. The master device communicates prefetch access requests to the slave memory based, at least in part, on the detected load state. Optionally, the master device communicates prefetch requests to the slave memory according to a schedule based, at least in part, on the detected load state.
摘要翻译： 从存储器的负载状态被检测并提供给主设备。 至少部分地基于检测到的负载状态，主设备将预取访问请求传送到从属存储器。 可选地，主设备至少部分地基于检测到的负载状态，根据调度将预取请求传送到从存储器。
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